Single polycrystalline silicon static FET flip flop memory cell

Claim 1

A memory cell structure on a substrate (38) of semiconductor material comprising first and second cross-coupled driver field effect transistors (16,18) and first and second load resistors (20,22) arranged in conjunction with a power supply line (24) and a ground line (26) to form a flip-flop (14), and first and second transfer transistors (28,30) arranged in conjunction with a word line (36) and first and second data lines (32,34) for accessing the flip-flop with data, characterized in that the components of the memory cell structure are formed in regions separated from each other by an insulation region (40) and in that the components comprise a first conductive region (42) formed in the substrate (32) to delineate the buried ground line (26) and the sources (46,50,54,58) and the drains (44,48,52,56) of the driver and the transfer transistors, the buried ground line (26) being connected to the source regions (46,50) of the first and second driver transistors (16,18); a second conductive region (60) formed within the insulation region (40) and above said first conductive region (42) to define a first portion (62) and a separated second portion (64), said first portion (62) delineating the word line (36) and the gate regions (66,68) of the transfer transistors, said second portion (64) delineating the gate regions (70,72) of the driver transistors, the first and second load resistors (20,22) and the power supply line (24), the power supply line (24) being oriented directly above and parallel to the buried ground line (26); said second portion (64) penetrating the insulation region (40) to said first conductive region (42) to form a first connection (80) and a second connection (78), said first connection (80) being between the source (58) of the second transfer transistor (30) and the gate (72) of the second driver transistor (18) and the drain (44) of the first driver transistor (16), said second connection (78) being between the source (54) of the first transfer transistor (28) and the gate (70) of the first driver transistor (16) and the drain (48) of the second driver transistor (18); and a metal region (84) formed on the surface of the insulation region (40) above said first-conductive region (42) and above said second conductive region (60) to delineate the first and second data lines (32,34), said metal region (84) penetrating the insulation region (40) to said first conductive region (42) to form a third connection (86) and a fourth connection (90), said third connection (86) being between the first data line (32) and the drain region of the first transfer transistor (28), said fourth connection (90) being between the second data line (34) and the drain region of the second transfer transistor (30).

Claim 8

A method of fabricating a bistable, flip-flop memory cell circuit comprising a pair of transfer transistors (28,30) and a pair of driver transistors (16,18) on a wafer (38) of semiconductor material, characterized in that the method comprises the steps of: growing a layer of insulation material onto the surface of the wafer (38) to form a selected pattern; doping a buried ground line (26) into a first non-insulated portion (42) of the wafer; depositing a layer (40) of insulation material over the entire wafer; etching off portions of the insulation material to expose first contact surfaces (74,76,82) on the drain and source regions; depositing a layer (60) of polycrystalline silicon on the wafer (38) to delineate a word line (36) and gate regions (66,68,70,72) of the transistors and to delineate a power supply line (24) and a pair of resistors (20,22) such that the power supply line (24) is directly above and oriented parallel to the buried ground line (26); doping drain and source regions for the transistors (16,18,28,30) into second portions (64) of the wafer, said pair of resistors (20,22)interconnecting respectively the source region (54,58) of a transfer transistor (28,30) and the drain region (44,48) of a driver transistor (16,18) and the gate region (70,72) of a driver transistor; depositing a layer (40) of insulation material on the wafer; etching off portions of the insulation material to expose second contact surfaces (88,92) on the drain regions (52,54); and depositing a metal layer (84) on the wafer to delineate a pair of data lines (32,34) connected to said second contact surfaces (88,92).

Claim 9

A method of fabricating a bistable, flip-flop memory cell circuit comprising a pair of transfer transistors (28,30) and a pair of driver transistors (16,18) on a wafer (38) of semiconductor material, characterized in that the method comprises the steps of: growing a layer of insulation material onto the surface of the wafer (38) to form a selected pattern; doping a buried ground line (26) into a first non-insulated portion (42) of the wafer; depositing a layer (40) of insulation material over the entire wafer; etching off portions of the insulation material to expose first contact surfaces (74,76,82) on the drain and source regions; depositing a layer (60) of polycrystalline silicon on the wafer (38) to delineate a word line (36) and gate regions (66,68,70,72) of the transistors and to delineate a power supply line (24) and a pair of resistors (20,22) such that the power supply line (24) is directly above and oriented parallel to the buried ground line (26); doping drain and source regions for the transistors (16,18,28,30) into second portions (64) of the wafer, said pair of resistors (20,22)interconnecting respectively the source region (54,58) of a transfer transistor (28,30) and the drain region (44,48) of a driver transistor (16,18) and the gate region (70,72) of a driver transistor; depositing a layer (40) of insulation material on the wafer; etching off portions of the insulation material to expose second contact surfaces (88,92) on the drain regions (52,54); and depositing a metal layer (84) on the wafer to delineate a pair of data lines (32,34) connected to said second contact surfaces (88,92).

Claim 12

A method as claimed in any of Claims 7 to 9, characterized in that said first portion (42) overlaps said second portions (64) at the source regions of the driver transistors.

Claim 13

A method as claimed in any of Claims 7 to 10, characterized in that before doping the drain regions and the source regions, enhancement regions (94,96) are implanted into portions of the wafer (38) between corresponding drain and source regions.

Claim 14

A method as claimed in any of Claims 7 to 11, characterized in that the first contact surfaces (74,76,82) exposed in said first etching step are on the drain regions of the driver transistors and on the source regions of the transfer transistors.

Claim 15

A method as claimed in any of Claims 7 to 12, characterized in that the step of depositing a layer of polycrystalline silicon to delineate components of the cell includes: depositing a layer of polycrystalline silicon over the entire wafer; selective N type doping of the polycrystalline silicon layer; etching off portions of the polycrystalline silicon layer; and N.type doping the remaining polycrystalline silicon layer except for the load resistor regions concurrently with the step of doping said drain and source regions.

Claim 16

A method as claimed in any of Claims 7 to 13, characterized in that the-'second contact surfaces (88,92) exposed in said second etching step are on the drain regions of the transfer transistors.

Claim 19

A method of fabricating a memory cell on a substrate (38) of semiconductor material, the memory cell comprising driver transistors (16,18), coupled t'o a power supply line (24) and a ground line (26), and transfer transistors (28,30) coupled to word and data lines (36,32, 34), characterized in that the method comprises the steps of doping selected areas of the substrate (38) to form a first conductive region (42) delineating the ground line (26) and first regions of the driver and transfer transistors (16,18, 28,30), depositing a first layer (40) of insulation material on the entire surface of the substrate (38) except for first exposed contact surfaces, depositing a second region (60) of conductive material on the substrate (38) to delineate the power supply line (24) and second regions of the driver and transfer transistors such that the power supply line (24) is directly above and oriented parallel to the ground line (26), depositing a second layer (40) of insulation material on the entire surface except for second exposed contact areas, and depositing a metal region (84) on the substrate to delineate data lines (32,34).

Claim 20

A method of fabricating a memory cell on a substrate (38) of semiconductor material, the memory cell comprising driver transistors (16,18), coupled t'o a power supply line (24) and a ground line (26), and transfer transistors (28,30) coupled to word and data lines (36,32, 34), characterized in that the method comprises the steps of doping selected areas of the substrate (38) to form a first conductive region (42) delineating the ground line (26) and first regions of the driver and transfer transistors (16,18, 28,30), depositing a first layer (40) of insulation material on the entire surface of the substrate (38) except for first exposed contact surfaces, depositing a second region (60) of conductive material on the substrate (38) to delineate the power supply line (24) and second regions of the driver and transfer transistors such that the power supply line (24) is directly above and oriented parallel to the ground line (26), depositing a second layer (40) of insulation material on the entire surface except for second exposed contact areas, and depositing a metal region (84) on the substrate to delineate data lines (32,34).