Abstract Data can be transferred across an interface between a computer processor (30) and a computer channel (32) by an associated pair of latches (34, 36 or 40, 38) for each direction of data flow. The integers on each side of the interface are supplied with a respective appropriate clock (C 1 or C 2 '). The clocks are dissimilar and non-harmonic, with periods T, and T 2 such that T 1 /T 2 is a rational number, and are offset by a delay circuit (D) by an amount less than Tn/a from the relationship in which simultaneous transitions would occur, a being the highest common factor of T 1 and T 2 , and a Tn being the synchronisation period of the two clocks.
Data transfer apparatus in which data is transmitted across an interface (Fig. 5) between parts (30, 32) of the apparatus operated under the control of two clocks (C 1 , C 2 ') with different frequencies, the clocks having two mutually non-harmonic frequencies whose periods T 1 and T 2 form a ratio that is a rational number, α being the highest common factor of T 1 and T 2 , so that there is a limited number of transitions of the pulses of each clock before pulse relationships of the two clocks are repeated, with a period α T , the two clocks being offset by an amount less than T n from the relationship in which simultaneous transitions would occur.
Claim 2
Dependent Claim
122 words
Data transfer apparatus in which data is transmitted across an interface (Fig. 5) between parts (30, 32) of the apparatus operated under the control of two clocks (C 1 , C 2 ') with different frequencies, the clocks having two mutually non-harmonic frequencies whose periods T 1 and T 2 form a ratio that is a rational number, α being the highest common factor of T 1 and T 2 , so that there is a limited number of transitions of the pulses of each clock before pulse relationships of the two clocks are repeated, with a period α T , the two clocks being offset by an amount less than T n from the relationship in which simultaneous transitions would occur.
Claim 3
Dependent Claim
53 words
Apparatus as claimed in claim 1 in which the two clocks comprise a first oscillator (56) and a second voltage controlled oscillator (50) operating respectively at f 1 = 1 and f2 = 1 , the second oscillator T, T 2 being sychronised with the first by phase lock loop circuitry (Fig. 6).
Claim 4
Dependent Claim
19 words
Apparatus as claimed in claim 2 in which the two clocks are offset by delay circuitry (D, Fig. 5).
Claim 5
Dependent Claim
21 words
Apparatus as claimed in claim 3 in which said delay circuitry (D) is connected to the output of the second" oscillator.
Claim 6
Dependent Claim
46 words
Apparatus as claimed in any preceding claim in which a pair of latches (38, 40; 34, 36) is provided for each direction of data flow across the interface, each latch of a pair receiving a respective one of the clocks (C 1 , C 2 ').
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