Patent EP0042552A2 successfully refreshed from Google Patents.
EP0042552A2
Expired / Lapsed
EP
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MOS type semiconductor device
Assignee: Toshiba Corp
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Filing: 1981-06-11
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Granted: —
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Expires: 2001-06-11
Abstract
Abstract An MOS type semiconductor device having a semiconductor substrate (21a, 21b), an insulating layer (22a,22b) formed in or on said semiconductor substrate (21a,21b), and an MOS transistor formed on said insulating layer (22a, 22b), characterized in that said insulating layer (22a, 22b) is formed at a region below said MOS transistor excluding at least part of the region below a channel region of said MOS transistor.
Inventors
- 👤 Hiroshi Hatano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 12:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0278; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D86/00; H10D86/201; H10D88/00; H10D88/01; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10D84/8311; H10D84/8312; H10D84/83138; H10W10/021; H10W10/20; Y; Y10; Y10S; Y10S257/00; Y10S257/901
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
69 words
. An MOS type semiconductor device having a semiconductor substrate (21a, 21b), an insulating layer (22a, 22b) formed in or on said semiconductor substrate (21a, 21b), and an MOS transistor formed on said insu-lating layer (22a, 22b), characterized in that said insulating layer (22a, 22b) is formed at a region below said MOS transistor excluding at least part of the region below a channel region of said MOS transistor.
Claim 2
Dependent Claim
69 words
. An MOS type semiconductor device having a semiconductor substrate (21a, 21b), an insulating layer (22a, 22b) formed in or on said semiconductor substrate (21a, 21b), and an MOS transistor formed on said insu-lating layer (22a, 22b), characterized in that said insulating layer (22a, 22b) is formed at a region below said MOS transistor excluding at least part of the region below a channel region of said MOS transistor.
Claim 3
Dependent Claim
31 words
An MOS type semiconductor device according to claim 1, characterized in that said insulating layer (22a, 22b) is formed at a region excluding part of the region below said channel region.
Claim 4
Dependent Claim
54 words
An MOS type semiconductor device according to claim 1, characterized in that said insulating layer (32) is formed at a region excluding the entire region below said channel region and part of a region adjacent to said entire region and below a source region (25) and a drain region (26) of the MOS transistor.
Claim 5
Dependent Claim
29 words
An MOS type semiconductor device according to any of claims 1 to 3, characterized in that said insulating layer (22a, 22b) is buried in said semiconductor substrate (21a, 21b).
Claim 6
Dependent Claim
51 words
An MOS type semiconductor device according to claim 1, characterized in that a memory cell is formed at a region of said semiconductor substrate in the vicinity of said MOS transistor, and apart as far as possible from said part of the region below the channel region of said MOS transistor.
Claim 7
Dependent Claim
42 words
An MOS type semiconductor device according to claim 1, characterized in that another MOS transistor is formed on said semiconductor substrate (41a), and said insulating layer (47) is formed on said other MOS transistor to provide a MOS transistor of stacked construction.
References Cited (Backward Citations)
No citation records indexed.
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