Patent EP0040251A1 successfully refreshed from Google Patents.
EP0040251A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1980-11-06
•
Granted: —
•
Expires: 2000-11-06
Abstract
Abstract A semiconductor memory device composed of double gate-type field effect transistors, each of which has a control gate (25), and a floating gate (23) that stores electric charges. The semiconductor memory device requires an arrangement of reciprocal structures, namely a structure adapted to inject charges into the floating gate of the memory device, and a structure adapted to read-out the stored information. To this end, the device employs an injection-only transistor (TrW) with a structure adapted for charge-injection and a read-only transistor (TrR) with a structure adapted for reading, the floating gates (23) of both the transistors being electrically coupled to each other, the control gates (25) thereof being connected to a first common signal-wire, the drains (22W,22R) thereof being connected to second-and third- different signal-wires, respectively, and the sources (21W,21R) thereof being grounded.
Inventors
- 👤 Koh-Ichi Maeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 22:27
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
125 words
1 . A semiconductor memory device providing the charge injection (write) transistor and read transistor which respectively have the source region and drain region having opposite conductivity type being formed in isolation on the substrate having the one conductivity type, the conductive floating gate which is formed between said source region and drain region and is electrically floated and the control gate which is isolated from said floating gate via the insulator, thus characterized in that; said floating gates of said charge injection transistor and read transistor are electrically connected, said control gates are connected in common to the first signal line, said drains are respectively connected to the different second and third signal lines, and said sources are connected to the first power supply.
Claim 2
Dependent Claim
125 words
1 . A semiconductor memory device providing the charge injection (write) transistor and read transistor which respectively have the source region and drain region having opposite conductivity type being formed in isolation on the substrate having the one conductivity type, the conductive floating gate which is formed between said source region and drain region and is electrically floated and the control gate which is isolated from said floating gate via the insulator, thus characterized in that; said floating gates of said charge injection transistor and read transistor are electrically connected, said control gates are connected in common to the first signal line, said drains are respectively connected to the different second and third signal lines, and said sources are connected to the first power supply.
Claim 3
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 1, thus characterized in that said charge injection (write) transistor and read transistor are respectively designed under the optimum design condition.
Claim 4
Dependent Claim
39 words
A semiconductor memory device as claimed ii'claim 2 thus characterized in that the impurity concentration of said substrate portion between said source region and drain region of said charge injection transistor is higher than that of said read transistor.
Claim 5
Dependent Claim
76 words
A semiconductor memory device as claimed in claim 1 thus characterized in that the charge is applied to the floating gate of said charge injection transistor by applying the specified voltage to said first signal line and the specified write voltage to the second signal line, and the stored information is read by applying the specified read voltage to said first signal line and detecting conductance degree said read transistor via the said third signal line.
Claim 6
Dependent Claim
54 words
A semiconductor memory device as claimed in claim 1, thus characterized in that said sources of said charge injection transistor and said.read transistor are composed of the common impurity diffused region, said floating gates are composed of the common first conductive layer and said control gates are composed of the common second conductive layer.
Claim 7
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 5 thus characterized in that said first conductive layer and the second conductive layer are composed of the poly-crystalline silicon layer.
Claim 8
Dependent Claim
92 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5 or 6, thus characterized in that the memory cells each of which has one said charge injection transistor and one said read transistor are arranged in the form of matrix, said first signal line is composed of the word lines arranged in the row direction, said second signal line is composed of the charge injection bit lines arranged in the column direction and said third signal line is composed of the read-out bit lines arranged in the column direction.
Claim 9
Dependent Claim
51 words
A semiconductor memory device as claimed in claim 7 thus characterized in that said word lines are composed of the poly-crystalline silicon layer, a part of said word lines is used as said control gates, and said charge injection bit lines and said read-out bit lines are composed of metal conductor.
Claim 10
Dependent Claim
81 words
A semiconductor memory device as claimed in claim 7, thus characterized in providing the column decoder circuit which connects, during the charge injection, the selected said charge injection bit lines and said charge injection circuit which generates the write voltage and also connects, at the time of read-out operation, selected said read-out bit lines and the sense circuit which detects conductance degree of said read transistor, and the word decoder circuit which applies the specified voltage to the selected word lines.
Claim 11
Dependent Claim
71 words
A semiconductor memory device as claimed in claim 1, 2, 3, 4, 5, or 6 thus characterized.in that the switching element additionally provided is connected to the second power supply via the drain load of said read transistor and said switching element is turned ON and OFF by making use of a difference in the potential levels of said load due to a difference of conductance degrees of said read transistor.
Claim 12
Dependent Claim
113 words
A semiconductor memory device as claimed in claim 10, thus characterized in that the compensating resistance is provided via said switching element to both or any one of the first resistor provided at the input portion of analog invertor circuit which outputs the signal inverted in the polarity from the input signal and the second resis - tor provided in the feed-back loop provided from the output portion to the input portion, and resistance value of said 1st resistor or the second resistor is compensated by injecting the charges to the specified said floating gate in accordance with the result of characteristic test and thereby changing the ON-OFF condition of said switching element.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.