PCM switching element

Claim 2

PCM switching element comprising means for converting the bits of incoming channels from series to parallel, a signal memory for storing the digital samples of the incoming channels, means for converting the bits of the outgoing channels from parallel to series, a control memory for storing the connections between incoming and outgoing channels, a control logic apt to receive and process data and commands coming from a control unit, and'timing means, characterized in that said control memory (MC) is able to store per each outgoing channel an additional bit ("busy" bit) sent by the control unit via the control logic (LC), having the task of causing within the time slots of one or more outgoing channels, to which it is associated at an appropriate logic level, the inhibiting of said means for converting from parallel to series (PS), in order to allow outgoing PCM groups of more switching elements to be connected in parallel, said inhibiting been achieved by replacing digital samples outgoing from said signal memory (MS) with words at constant logic level.

Claim 3

PCM switching element as in claim l, characterized in that said control logic (LC) capable of receiving data and commands directly from an asynchronous control-unit on parallel data-bus and on control bus, comprises: - a plurality of registers (Rl, R2, R3, R4), capable of memorizing the data coming from the control unit and containing in order the identifications of the incoming group, of the incoming channel, of the outgoing group and of the outgoing channel; - a 1 -to-4-line demultiplexer (Dl), capable of enabling said plurality of registers, in function of the code associated with the data coming from the control unit; - a register (R5) for storing the type of operation to be carried out by the PCM switching element; - a plurality of multiplexers (S1, S2, S3, S4), apt to transfer to their outputs the data sent by said plurality of registers pr the cyclical addresses sent by said timing means (BT), according to the operation to carry out, the outputs of said plurality of multiplexers being connected to data and address inputs of the control memory; - a control circuit for the inputs (Pl, P2, P3, Fl, F2), which, upon commands arriving from the control unit and meaning transfer request of the data from data bus to the PCM switching element, generates in synchronism with the internal timing signals an enabling signal to data storage in said plurality of registers and in said register; - a circuit for the control of said plurality of multiplexers and for the transfer of the write pulses into the control memory, consisting both of a decoder (D2), that depending on the code of the requested operation sets a plurality of flip-flops (F3, F4, F5) to appropriate logic states, said flip-flops being capable of driving select inputs of said plurality of multiplexers through a combinational circuit (01, Q2, P7, P8, P9, P10), and of a first flip-flop (F6) capable of storing the codes of the operations requiring more than one writing in the control memory and of a second flip- flop (F7), capable of storing said additional bit ("busy" bit) present at an output of said register (R5), and also of a firjt and second gates (P4, P5), able to control the transfer of the write pulses into the control memory, and of a third gate (P6), able to reset said register (R5) in function of the type of operation carried out.

Claim 4

PCM switching element as in claims 1 and 2, characterized in that: - to carry out a first connecting operation of any incoming channel with an outgoing one upon reception of an appropriate message from the control unit, a first and a fourth (Sl, S4) of said plurality of multiplexers are switched in such a way that during the write phase the signals coming from a first and a fourth (Rl, R4) of said plurality of regi sters may be transferred to control memory, the additional bit coming from said register (R5) is stored in said second flip-flop (F7) and a single write pulse is present at the output of said second gate (P5); - to carry out a second disconnecting operation consisting of inhibiting of any outgoing channel, a third and a fourth (S3, S4) of said plurality of multiplexers are switched during the write phase in control memory so as to transfer the signals arriving from a third and fourth (R3, R4) of said plurality of registers, the additional bit stored in the second flip-flop is at a logic level corresponding to inhibiting of the wanted outgoing channel and at the output of said second gate (P5) a single write pulse is present; - to carry out a third inhibiting operation of all the outgoing channels, the third and the fourth of said plurality of multiplexers transfer the addresses coming from said timing means (BT) during the write phase in control memory, the additional bit , stored in the second flip-flop at a logic level corresponding to inhibiting, is written in all the cells of the control memory and at the output of the second gate there are present as many write pulses as are the cells in control memory; - to carry out a fourth connecting operation of all the incoming. channels with all the outgoing channels in the write phase the first and a second (Sl, S2) of said plurality of multiplexers are switched so as to transfer the signals arriving from the first and second (Rl, R2) of said plurality of registers and the third and fourth of said plurality of multiplexers are switched so as to transfer the addresses coming from said timing means, the additional bit stored in the second flip-flop allows all the outgoing channels to be enabled, and at the output of the second gate there are as many write pulses as are the cells in the control memory; - to carry out a fifth connecting operation of the incoming channels with all the corresponding outgoing channels, the first and fourth of said plurality of multiplexers are switched so as to transfer during the write phase the addresses coming from said timing means, the additional bit stored in the second flip-flop enables all the outgoing channels, and at the output of the second gate there are as many write pulses as are the cells in the control memory; - to carry out a sixth connecting operation of all the channels of any incoming group with all the corresponding channels of any outgoing group, during the write phase the first and third of said plurality of multiplexers are switched so as to transfer the signals coming from the first and third of said plurality of registers, the second and fourth of said plurality of multiplexers are switched so as to transfer the addresses arriving from those timing means, the additional bit stored in the second flip-flop enables all the channels of the addressed outgoing group and at the output of the second gate there are present as many write pulses as are necessary to update the cells of the control memory corresponding to the channels of the outgoing group.

Claim 5

PCM switching element as in claims I and 2, characterized in that it comprises an initializing circuit, activated by a single control signal for inhibiting all the outgoing channels and consisting of a third flip-flop (F8), that stores said control signal and sends it to a synchronizing circuit (F9, F10, Pll), that renders it wide as and in phase with the timing period, and acting upon said first and second flip-flops(F6, F7) causes the additional bit to be stored at the logic state in which all outgoing channels are inhibited, at the output of the second gate (P5) there are present as many write pulses as . are the cells of the control memory and the third and the fourth (S3, S4) of said plurality of multiplexers are switched so as to transfer the addresses arriving from the timing means (BT).

Claim 6

PCM switching element as in claim 1, characterized in that said means (SP, PS) for converting the bits of incoming channels from series to parallel and the bits of outgoing channels from parallel to series are transposition matrices with a number of rows equal to the number of groups and a number of columns equal to the number of bits of each channel.

Claim 7

PCM switching element as in claims 1 and 2, characterized in that said control logic (LC) is designed to process data and commands arriving from a control unit consisting of a microprocessor.

Claim 8

PCM switching element as in claim 1, characterized in that it is made as an integrated circuit.

Claim 9

PCM switching element as in claim 1, characterized in that it is designed to be connected with other similar PCM switching elements to make a higher-capacity connecting matrix for sets of n incoming and m outgoing groups, that is organized in m rows and n columns, it presents a single data and command bus (117), obtained by placing in parallel the buses of each element and has the cross points between sets of rows and columns consisting of PCM switching elements having the inputs in parallel, if pertaining to the same column (E Cl, EC2), and the outputs in parallel, if pertaining to the same row (EC3, EC4), said sets of groups consisting of as many groups as are the inputs or the outputs of an element.

Claim 10

PCM switching element as in claim 1, characterized in that it is designed to be connected with other similar PCM switching elements to make a concentration stage betweenp incoming groups and q outgoing groups, where the number of elements (ECS, EC6, EC7) is such that there are as many inputs as are the p incoming groups, whereas the q outgoing groups are obtained by placing in parallel as many corresponding outputs of different elements and the data and control bus (325) of the concentration stage is obtained by placing in parallel the buses of each element.

Claim 11

PCM switching element basically as described in the text and depicted in the annexed drawings.

Claim 12

PCM switching element basically as described in the text and depicted in the annexed drawings.