Process for fabricating an integrated PNP and NPN transistor structure

Claim 2

In an integrated circuit structure including an NPN transistor and a PNP transistor, said structure including a silicon substrate (1) having a planar surface including a thin epitaxial layer (3), said epitaxial layer having recessed oxide isolation regions and P type polysilicon regions formed therein, said integrated circuit structure being characterized by - a first electrically isolated P type polysilicon region formed in said epitaxial layer (3) and having at least one perpendicular side wall; - a second electrically isolated P type polysilicon region formed in said epitaxial layer (3) and having at least one perpendicular side wall; said side wall of said second P type polysilicon region being oppositely disposed and spaced from said side wall of said first P type polysilicon region; - said spacing between said perpendicular side walls of said P type polysilicon regions providing a region of said epitaxial layer (3) having a width of approximately 0 8000A; 0 - a lateral PNP transistor formed in said 8000A wide region of said epitaxial layer(3), where said first P type polysilicon region is utilized in providing an electrical contact to said emitter of said lateral PNP transistor and said second P type polysilicon region is utilized in providing an electrical contact to said collector of said PNP transistor.

Claim 3

In an integrated circuit structure including an NPN transistor and a PNP transistor, as recited in claim 1, wherein said structure is further characterized in that an N type base reach through region for said PNP transistor is provided in said epitaxial layer (3), said N type base reach through region being remote from and electrically isolated from said first and second electrically isolated P type polysilicon regions.

Claim 4

In an integrated circuit structure including an NPN transistor and a PNP transistor, as recited in claim 2, further characterized in that said NPN transistor includes:a shallow depth emitter region of limited area, said emitter region having an exposed planar surface;a shallow depth base region of limited area, said base region providing an essentially planar emitter-base junction, said base region having a contact region laterally displaced from said emitter-base junction;and a third electrically isolated P type polysilicon region 'formed in said epitaxial layer, said third polysilicon region extending from said base region of said NPN transistor and physically and electrically contacting said laterally displaced base contact region.

Claim 5

In an integrated circuit structure including an NPN transistor and a PNP transistor as recited in claim 3, further characterized in that an N type collector reach through region for said NPN transistor is provided in said epitaxial layer (3) , said N type collector reach through region being remote from and electrically isolated from said first, second and third electrically isolated P type polysilicon regions.

Claim 6

Process for forming on a planar surface of a P type silicon substrate an improved NPN transistor and an improved PNP. transistor, characterized by the following steps: (a) form an N type region (2) in said planar surface of said P type silicon substrate (1); (b) form a thin epitaxial layer (3) of N type silicon on said surface of said substrate (1); (c) form a silicon dioxide layer (4) on said substrate surface; (d) form a silicon nitride layer (5) on said substrate (1); (e) form a polysilicon layer (6) of limited area and defined placement on said substrate surface; (f) form a CVD silicon dioxide layer on said substrate surface, said silicon dioxide layer (4) having a 0 thickness in the order of 8000A; (g) blanket reactive ion etch said substrate surface to said polysilicon region (6') and said silicon nitride layer (5); (h) remove said polysilicon layer (6), said silicon nitride layer (5) and said silicon dioxide layer (4) whereby an accurately placed mask (8) having 0 a width in the order of 8000A is provided;and (i) additional processing to provide an NPN and a PNP transistor wherein said active emitter base and collector regions of said PNP transistor are defined in said thin epitaxial layer within a 0 width in the order of 8000A.

Claim 7

Process for forming on a planar surface of a P type silicon substrate an improved NPN transistor and an improved PNP. transistor, characterized by the following steps: (a) form an N type region (2) in said planar surface of said P type silicon substrate (1); (b) form a thin epitaxial layer (3) of N type silicon on said surface of said substrate (1); (c) form a silicon dioxide layer (4) on said substrate surface; (d) form a silicon nitride layer (5) on said substrate (1); (e) form a polysilicon layer (6) of limited area and defined placement on said substrate surface; (f) form a CVD silicon dioxide layer on said substrate surface, said silicon dioxide layer (4) having a 0 thickness in the order of 8000A; (g) blanket reactive ion etch said substrate surface to said polysilicon region (6') and said silicon nitride layer (5); (h) remove said polysilicon layer (6), said silicon nitride layer (5) and said silicon dioxide layer (4) whereby an accurately placed mask (8) having 0 a width in the order of 8000A is provided;and (i) additional processing to provide an NPN and a PNP transistor wherein said active emitter base and collector regions of said PNP transistor are defined in said thin epitaxial layer within a 0 width in the order of 8000A.

Claim 8

In a process as recited in claim 5 wherein said CVD silicon dioxide layer in step (f) is in the order of 6000A in thickness and said active emitter, base and collector regions of said PNP transistor are contained within a region of said thin epitaxial layer having a width in the order of 6000A.

Claim 9

Process for forming on a planar surface of a P type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, characterized by the following steps: • (a) form an N type region (2, Fig. 1) in said planar surface of said P type silicon substrate; (b) form a thin epitaxial layer (3, Fig. 1) of N type silicon on said surface of said substrate; (c) form a thin silicon dioxide layer (4, Fig. 1) on said exposed surface of said substrate; (d) form a silicon nitride layer (5, Fig. 1) on said exposed surface of said substrate; (e) form a polysilicon layer (6, Fig. 1) on said exposed surface of said substrate; (f) remove all but a predetermined portion (6', Fig.

Claim 10

Process for forming on a planar surface of a P type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, characterized by the following steps: • (a) form an N type region (2, Fig. 1) in said planar surface of said P type silicon substrate; (b) form a thin epitaxial layer (3, Fig. 1) of N type silicon on said surface of said substrate; (c) form a thin silicon dioxide layer (4, Fig. 1) on said exposed surface of said substrate; (d) form a silicon nitride layer (5, Fig. 1) on said exposed surface of said substrate; (e) form a polysilicon layer (6, Fig. 1) on said exposed surface of said substrate; (f) remove all but a predetermined portion (6', Fig.

Claim 11

2) of said polysilicon layer (6); (g) chemically vapor deposit a silicon dioxide layer (7, Fig. 7) on said exposed surface of said substrate; (h) reactive ion etch the exposed surface of said substrate to expose the surface of said polysilicon region (6', Fig. 4) and said surface of said silicon nitride layer (5, Fig. 4); (i) remove said polysilicon region (6'); (j) remove the exposed portion of silicon nitride layer (5); (k) provide a mask (8, Fig. 5) having windows Wl and W2 and wherein said window W2 has a block out frame "B"; (1) utilizing said mask having windows Wl, W2 and block out frame "B", remove the exposed portions of the silicon dioxide layer (4, Fig. 5); (m) remove the mask (8); (n) utilizing the remaining portion of the silicon dioxide layer (4) and blockout frame "B" as a block out mask provide shallow trenches (ST1, ST2 and ST3, Fig. 6); (o) remove the remaining portion of silicon dioxide layer (4) and blockout frame "B" (Fig. 6); (p) chemically vapor deposit a layer of silicon dioxide layer (9, Fig. 7) on the exposed surface of the substrate; (q) form a mask (10, Fig. 7) having windows W3, W4 and W5; (r) utilize reactive ion etching to remove the portions of silicon dioxide layer (9, Fig. 7) exposed by windows W3, W4 and W5 of the mask (10); (s) remove mask (10); (t) utilize reactive ion etching and the windows W3, W4 and W5 in silicon dioxide layer (9) to provide deep trenches DTl, DT2 and DT3 in the exposed surface of the substrate (Fig. 8); (u) remove the remaining portion of silicon dioxide layer (9, Fig. 8); (v) thermally oxidize the exposed surface of the substrate to provide oxide layer (11, Fig. 9); (w) form a relatively thick oxide layer (12, Fig. 10) on the exposed surface of the substrate, said relatively thick oxide layer (12) filling said shallow trenches (ST1, ST2 and ST3), said deep trenches (DTl, DT2 and DT3) and tending to planarize said exposed surface of said substrate; (x) utilizing a photoresist material (13, Fig. 10) planarize the exposed surface of the substrate; (y) utilize reactive ion etching to thin back the exposed surface of the substrate to the surface of the epitaxial layer (3, Fig. 11); (z) form a block out mask (14, Fig. 12) to block out a predetermined region (B, Fig. 11) of the epitaxial layer; (a-l)ion implant arsenic ions, , into the ex posed regions of the epitaxial layer (Fig. 12), the regions implanted with arsenic are the emitter of the NPN device, the reach through reach region of the NPN device, and the reach through region of the PNP device (Fig. 12); (b-l)form a block out mask (15, Fig. 13) to block out predetermined portions of said epitaxial layer; (c-l)ion implant phosphorous ions, P + , into the exposed surface of the substrate; (d-l)remove the block-out mask (15); (e-l)form a mask (16, Fig. 14) having windows (W6 and W7); (f-1)utilize a silicon dioxide etchant to provide recesses (Rl, R2 and R3, Fig. 15) in the exposed surface of the substrate; (g-l)vacuum evaporate a platinum, Pt, film (17, Fig.16) on the exposed surface of the substrate; (h-l)etch the exposed surface of the substrate with an etchant which etches N regions (18, 20, Fig. 17) at greater rate than N region (19, Fig. 17), the etching being terminated when the N + regions, as compared to the N region, are over etched a predetermined depth; (i-1)remove the platinum, Pt, film; (j-l)thermally oxidize the exposed surface of the substrate to provide a relatively thick oxide layer (21, Fig. 18) on the exposed N + regions and a relatively thin oxide layer on the N regions; (k-l)remove the relatively thin oxide layer on the N regions; (1-1)chemically vapor deposit a silicon nitride, Si 3 N 4 film (22, Fig. 19) on the exposed surface of the substrate; (m-l)convert the silicon nitride Si 3 N 4 film (22) on the N regions to anodic silicon dioxide; (n-1)remove the anodic silicon dioxide from the N regions; (o-l)chemically vapor deposit a relatively thick P polysilicon layer (23, Fig. 20) on the exposed surface of the substrate, said relatively thick P polysilicon layer filling said recesses Rl, R2 and R3 (Fig.19); (p-l)utilizing a photoresist material (24, Fig. 20) planarize the exposed surface of the substrate; and (q-1)utilize reactive ion etching to thin back the exposed surface of the substrate to the silicon nitride film (22, Fig. 21).

Claim 12

2) of said polysilicon layer (6); (g) chemically vapor deposit a silicon dioxide layer (7, Fig. 7) on said exposed surface of said substrate; (h) reactive ion etch the exposed surface of said substrate to expose the surface of said polysilicon region (6', Fig. 4) and said surface of said silicon nitride layer (5, Fig. 4); (i) remove said polysilicon region (6'); (j) remove the exposed portion of silicon nitride layer (5); (k) provide a mask (8, Fig. 5) having windows Wl and W2 and wherein said window W2 has a block out frame "B"; (1) utilizing said mask having windows Wl, W2 and block out frame "B", remove the exposed portions of the silicon dioxide layer (4, Fig. 5); (m) remove the mask (8); (n) utilizing the remaining portion of the silicon dioxide layer (4) and blockout frame "B" as a block out mask provide shallow trenches (ST1, ST2 and ST3, Fig. 6); (o) remove the remaining portion of silicon dioxide layer (4) and blockout frame "B" (Fig. 6); (p) chemically vapor deposit a layer of silicon dioxide layer (9, Fig. 7) on the exposed surface of the substrate; (q) form a mask (10, Fig. 7) having windows W3, W4 and W5; (r) utilize reactive ion etching to remove the portions of silicon dioxide layer (9, Fig. 7) exposed by windows W3, W4 and W5 of the mask (10); (s) remove mask (10); (t) utilize reactive ion etching and the windows W3, W4 and W5 in silicon dioxide layer (9) to provide deep trenches DTl, DT2 and DT3 in the exposed surface of the substrate (Fig. 8); (u) remove the remaining portion of silicon dioxide layer (9, Fig. 8); (v) thermally oxidize the exposed surface of the substrate to provide oxide layer (11, Fig. 9); (w) form a relatively thick oxide layer (12, Fig. 10) on the exposed surface of the substrate, said relatively thick oxide layer (12) filling said shallow trenches (ST1, ST2 and ST3), said deep trenches (DTl, DT2 and DT3) and tending to planarize said exposed surface of said substrate; (x) utilizing a photoresist material (13, Fig. 10) planarize the exposed surface of the substrate; (y) utilize reactive ion etching to thin back the exposed surface of the substrate to the surface of the epitaxial layer (3, Fig. 11); (z) form a block out mask (14, Fig. 12) to block out a predetermined region (B, Fig. 11) of the epitaxial layer; (a-l)ion implant arsenic ions, , into the ex posed regions of the epitaxial layer (Fig. 12), the regions implanted with arsenic are the emitter of the NPN device, the reach through reach region of the NPN device, and the reach through region of the PNP device (Fig. 12); (b-l)form a block out mask (15, Fig. 13) to block out predetermined portions of said epitaxial layer; (c-l)ion implant phosphorous ions, P + , into the exposed surface of the substrate; (d-l)remove the block-out mask (15); (e-l)form a mask (16, Fig. 14) having windows (W6 and W7); (f-1)utilize a silicon dioxide etchant to provide recesses (Rl, R2 and R3, Fig. 15) in the exposed surface of the substrate; (g-l)vacuum evaporate a platinum, Pt, film (17, Fig.16) on the exposed surface of the substrate; (h-l)etch the exposed surface of the substrate with an etchant which etches N regions (18, 20, Fig. 17) at greater rate than N region (19, Fig. 17), the etching being terminated when the N + regions, as compared to the N region, are over etched a predetermined depth; (i-1)remove the platinum, Pt, film; (j-l)thermally oxidize the exposed surface of the substrate to provide a relatively thick oxide layer (21, Fig. 18) on the exposed N + regions and a relatively thin oxide layer on the N regions; (k-l)remove the relatively thin oxide layer on the N regions; (1-1)chemically vapor deposit a silicon nitride, Si 3 N 4 film (22, Fig. 19) on the exposed surface of the substrate; (m-l)convert the silicon nitride Si 3 N 4 film (22) on the N regions to anodic silicon dioxide; (n-1)remove the anodic silicon dioxide from the N regions; (o-l)chemically vapor deposit a relatively thick P polysilicon layer (23, Fig. 20) on the exposed surface of the substrate, said relatively thick P polysilicon layer filling said recesses Rl, R2 and R3 (Fig.19); (p-l)utilizing a photoresist material (24, Fig. 20) planarize the exposed surface of the substrate; and (q-1)utilize reactive ion etching to thin back the exposed surface of the substrate to the silicon nitride film (22, Fig. 21).

Claim 13

In a process for forming on a planar surface of a P type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 7, wherein in step (b) said epitaxial layer (3, Fig. 1) has an N type doping in the order of 2 x 1 0 16 atoms of arsenic per cubic centimeter and a thickness in the order of two micrometers.

Claim 14

In a process for forming on a planar surface of a P type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 8, wherein in step (c) said thin silicon dioxide layer (4, Fig. 1) has a thickness in the order of 200 nanometers and in step (d) said silicon nitride layer (5, Fig. 1) has a thickness in the order of 100 nanometers.

Claim 15

In a process for forming on a planar surface of a P-type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 8, wherein in step (e) said polysilicon layer (6, Fig. 1) preferably has a thickness in the order of 600 to 700 nanometers.

Claim 16

In a process for forming on a planar surface of a P-type silicon transistor and an improved PNP transistor, as recited in claim 10, wherein in step (g) said chemically vapor deposited silicon dioxide layer (7, Fig. 3) is deposited at a temperature in the order of 800 to 900°C and said silicon dioxide layer has a thickness in the order of 800 nanometers.

Claim 17

In a process for forming on a planar surface of a P-type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 11, wherein in step (k) said blockout frame ° "B" has a width in the order of 6000 to 8000A.

Claim 18

In a process for forming on a planar surface of a P-type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 7, wherein in step (h-1) the etchant employed is preferably a mixture HF:HN0 3 :CH 3 COOH = 1:3:8.

Claim 19

In a process for forming on a planar surface of a P-type silicon substrate (1, Fig. 1) an improved NPN transistor and an improved PNP transistor, as recited in claim 13, wherein in step (g-1) a film other than platinum is employed, said film employed having the characteristic of not being chemically attached by said etchant employed in subsequent step (h-1).

Claim 20

In a process for forming on a planar surface of a P-type silicon substrate an improved PNP transistor, said process being characterized by the forming of an accurately dimensioned blockout mask having a width in the ° order of 6000 to 8000A and the utilization of said blockout mask to provide an accurately dimensioned region of an epitaxial layer, said accurately dimensioned region of said epitaxial layer having a width equal to that of said blockout mask.

Claim 21

In a process for forming on a planar surface of a P-type silicon substrate an improved PNP transistor, said process being characterized by the forming of an accurately dimensioned blockout mask having a width in the ° order of 6000 to 8000A and the utilization of said blockout mask to provide an accurately dimensioned region of an epitaxial layer, said accurately dimensioned region of said epitaxial layer having a width equal to that of said blockout mask.

Claim 22

In a process for forming on a planar surface of a P-type silicon substrate an improved PNP transistor, as recited in claim 15, said process being further characterized by the forming of said PNP transistor within said accurately dimensioned region of said epitaxial layer.

Claim 23

In a process for forming on a planar surface of a P-type silicon substrate an improved PNP transistor, as recited in claim 16, further characterized in that said process, concurrently with the forming of said improved PNP transistor, forms an improved NPN transistor.