Patent EP0039177A2 successfully refreshed from Google Patents.
EP0039177A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A solid-state imaging device
Assignee: Hitachi Ltd
•
Filing: 1981-04-15
•
Granted: —
•
Expires: 2001-04-15
Abstract
Abstract A solid-state imaging device which has a plurality of photodiodes (74,75) which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements (8) and a group of vertical switching elements (47) which energize the photodiodes, and a horizontal scanning circuit (41) and a vertical scanning circuit (42) which impress scanning pulses on the horizontal and vertical switching elements respectively. The device also has an interlaced scanning mechanism (53) which energizes a plurality of vertical scanning lines (48) by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows. The interlaced scanning mechanism (53) includes insulated-gate field effect transistors (66, 67) for recovering voltage levels of the scanning pulses having undergone voltage drops due to MOSTs (56, 57) in an interlace switching circuit (52).
Inventors
- 👤 Masakazu Aoki
- 👤 Haruhisa Ando
- 👤 Shinya Ohba
- 👤 Shoji Hanamura
- 👤 Iwao Takemoto
- 👤 Ryuichi Izawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 06:42
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H04; H04N; H04N25/00; H04N25/70; H04N25/76; H04N25/78
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
129 words
A solid-state imaging device including a plurality of photodiodes (75) which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements (8) and a group of vertical switching elements (47) which energize the photodiodes, a horizontal scanning circuit (41) and a vertical scanning circuit (42) which apply scanning pulses to the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism (43) which energizes a plurality of vertical scanning lines (48) by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows.; characterized in that said interlaced scanning mechanism includes means (53) to recover a voltage level of the scanning pulse having undergone a voltage drop due to said interlace switching elements.
Claim 2
Dependent Claim
129 words
A solid-state imaging device including a plurality of photodiodes (75) which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements (8) and a group of vertical switching elements (47) which energize the photodiodes, a horizontal scanning circuit (41) and a vertical scanning circuit (42) which apply scanning pulses to the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism (43) which energizes a plurality of vertical scanning lines (48) by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows.; characterized in that said interlaced scanning mechanism includes means (53) to recover a voltage level of the scanning pulse having undergone a voltage drop due to said interlace switching elements.
Claim 3
Dependent Claim
64 words
A solid-state imaging device according to Claim 1, characterized in that said interlaced scanning mechanism includes an interlace circuit (52) which changes-over a combination of the vertical scanning lines to be energized by means of interlace switching elements (56, 57) every field, and a vertical buffer circuit (53) which recovers the voltage level of the scanning pulse having passed through said interlace circuit (52).
Claim 4
Dependent Claim
92 words
A solid-state imaging device according to Claim 2, characterized in that said vertical buffer circuit (53) includes insulated-gate field effect transistors (66, 67) for recovering voltage drops which are arranged at the respective vertical scanning lines, which receive output signals from said interlace circuit (52) as their gate inputs and which are driven by driving pulses synchronous with output pulses of said vertical scanning circuit, and capacitances (70, 71) which contribute to the bootstrap effect exist between the gates and sources of said insulated-gate field effect transistors-(66, 67) for recovering voltage drops.
Claim 5
Dependent Claim
150 words
A solid-state imaging device according to Claim 2, characterized in that said interlace circuit (52) includes first to fourth switching elements which consist of insulated-gate field effect transistors (56, 57) connected at the outputs of respective stages of unit circuits (51) constituting said vertical scanning circuit (50) and which permit the simultaneous horizontal scanning of the scanning lines of two rows, first and second field pulses being respectively applied to a set of said first and second switching elements and a set of said third and fourth switching elements, said first and second switching elements being operated in a first field and said third and fourth switching elements in a second field by the use of output pulses provided from said vertical scanning circuit in timed sequence with said field pulses, in order to generate gate input pulses to.said insulated-gate field effect transistors so as to recover the voltage drops.
Claim 6
Dependent Claim
209 words
` 5. A solid-state imaging device according to Claim 2, characterized in that the sources (or drains) of the first to fourth switching elements are connected to the outputs of the respective stages of said unit circuits (51) constituting said vertical scanning circuit (50); the drain (or source) of said first switching element (57), the drains (or sources) of said second and third switching elements (56) and the drain (or source) of said first switching element (57) are respectively connected to the gates of the insulated-gate field effect transistors (66 and 67) for recovering the voltage drops, of the vertical scanning lines of a first row, second row and third row corresponding to the stages of said unit circuits; the field pulses being applied to the gates of said first to fourth switching elements; the drains (or sources) of said insulated-gate field effect transistors (66, 67) for recovering the voltage drops being connected to a first common line (60), on which driving pulses (φ B1 ) synchronous with output pulses provided from said vertical scanning circuit in timed sequence are applied; and the sources (or drains) of said insulated-gate field effect transistors (66, 67) for recovering the voltage drops being connected to the respective vertical scanning lines (64, 65).
Claim 7
Dependent Claim
93 words
A solid-state imaging device according to Claim 5, characterized in that the drains (or sources) of further insulated-gate field effect transistors (68) for resetting whose gates are connected to a second common line (61) and whose sources (or drains) are connected to a third common line (62),are connected to the sources (or drains) of said insulated-gate field effect transistors (66, 67) for recovering the voltage drops, a reset pulse (; B2 ) being applied to said second common line (61) and said third common line (62) being earthed or held at zero volts.
Claim 8
Dependent Claim
48 words
A solid-state imaging device according to any one of the preceding Claims 2 to 6, characterized in that said vertical and horizontal switching elements are constructed of insulated-gate field effect transistors, and source junctions of said vertical switching elements (72, 73) are employed as said photodiodes (74, 75).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.