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EP0036185A2
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Information processing system incorporating 1-chip arithmetic control unit of very large scale integrated semiconductor element
Assignee: Toshiba Corp
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Filing: 1981-03-12
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Granted: —
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Expires: 2001-03-12
Abstract
Abstract in an information processing unit in which an arithmetic control unit (101) is formed on one chip by a very large scale integrated semiconductor element and is connected to external devices through a common bus (103) the microinstruction from the externally attached control memory (102), and the memory information and the output information from the external main memory and the I/O devices, can be received by the arithmetic control unit (101) through the common bus (103). Further external setting signal for selecting whether the instruction system of the arithmetic control unit (101) is to be effective or ineffective is received by the arithmetic control unit (101) through the common bus (103) simultaneously with the fetching of the microinstruction. A bus width setting signal from the I/O is also received by the arithmetic control unit (101) through the common bus (103) simultaneously with the fetching of the microinstruction, and it is judged whether the data width from the I/O is 8 bits or 16 bits. An interruption signal from an I/O and a signal indicating an abnormal condition of the power source may be received by the arithmetic control unit (101) from the external devices through the common bus (103) simultaneously with the fetching of the microinstruction. When exchanging a plurality of kinds of data with different phases between the arithmetic control unit (101) and the external devicesthrough the common bus (103), an external status signal particular to each phase is received by the arithmetic control unit (101) through a common signal line in synchronism with the phase.
Inventors
- 👤 Tsuneo Kinoshita
- 👤 Fumitaka Sato
- 👤 Isamu Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
209 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit of a very large scale integrated semiconductor element; an external control memory in which are stored a plurality of microprograms consisting of a plurality of microinstructions for controlling said arithmetic control unit; means for accessing said control memory in response to a microinstruction address output from said arithmetic control unit; a common bus connecting said arithmetic control unit, a memory bus, and an input/output bus; means for separating said common bus into a bus at the side of said arithmetic control unit and a bus at the side of an external devices connected to said memory bus and said input/output bus in response to a signal instructing the reception of said microinstruction output from said arithmetic control unit; means for transferring said microinstruction to said arithmetic control unit, said microinstruction being read out from said control memory through the bus at the side of said arithmetic control unit when said common bus is separated by said separating means; and means for connecting said memory buses, said input/output bus and said common bus, and for performing data transfer between said arithmetic control unit and said external devices when said common bus is not separated.
Claim 2
Dependent Claim
209 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit of a very large scale integrated semiconductor element; an external control memory in which are stored a plurality of microprograms consisting of a plurality of microinstructions for controlling said arithmetic control unit; means for accessing said control memory in response to a microinstruction address output from said arithmetic control unit; a common bus connecting said arithmetic control unit, a memory bus, and an input/output bus; means for separating said common bus into a bus at the side of said arithmetic control unit and a bus at the side of an external devices connected to said memory bus and said input/output bus in response to a signal instructing the reception of said microinstruction output from said arithmetic control unit; means for transferring said microinstruction to said arithmetic control unit, said microinstruction being read out from said control memory through the bus at the side of said arithmetic control unit when said common bus is separated by said separating means; and means for connecting said memory buses, said input/output bus and said common bus, and for performing data transfer between said arithmetic control unit and said external devices when said common bus is not separated.
Claim 3
Dependent Claim
40 words
A system according to claim 1, characterized in that the data width of said common bus is N bits and an instruction word of the microinstruction read out ' from said control memory is M bits where M < N.
Claim 4
Dependent Claim
53 words
A system according to claim 1, characterized in that said microinstruction of M bits read out from said control memory and a group of external signals of K bits are simultaneously transferred to said arithmetic control unit through said common bus of data width of N bits where N = M + K.
Claim 5
Dependent Claim
45 words
A system according to claim 3, characterized in that two groups of external signals are included and either of said two groups of external signals is selected by a selection signal output from said arithmetic control unit to be transferred to said arithmetic control unit.
Claim 6
Dependent Claim
30 words
A system according to claim 4, characterized in that either of said two groups of external signals is received by said arithmetic control unit only during initialization of said system.
Claim 7
Dependent Claim
30 words
A system according to claim 1, characterized in that input/output devices capable of inputting/output- ting data of L or 2L bits by one operation are connected to said input/output bus.
Claim 8
Dependent Claim
64 words
A system according to claim 3 or 6, characterized in that means is provided for setting a signal for designating a bit number of the input/output data of said input/output devices connected to said input/output bus, and the signal set by said signal setting means as one of said groups of external signals is received by said arithmetic control unit simultaneously with said microinstruction.
Claim 9
Dependent Claim
39 words
A system according to claim 1, characterized in that said memory bus comprises a memory address line and a memory data line, and a main memory operating asynchronously with said arithmetic control unit is connected to said memory bus.
Claim 10
Dependent Claim
29 words
A system according to claim 8, characterized in that said arithmetic control unit transits to a next operation in response to an access completion signal from said main memory.
Claim 11
Dependent Claim
69 words
A system according to claim 3 or 9, characterized in that means is incorporated for judging whether or not to signal as an error when said access completion signal is not input to said arithmetic control unit within a certain period of time, and a signal from said means is received by said arithmetic control unit, as one of said groups of external signals, simultaneously with said microinstruction. 10,
Claim 12
Dependent Claim
190 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit'of a very large scale integrated semiconductor element; a first control memory in which are stored a plurality of microprograms consisting of a plurality of microinstructions connected externally to said arithmetic control unit for controlling it; a second control memory which is disposed inside said arithmetic control unit and in which is stored one of an identifier indicating that microinstruction processing may be completed in one step, an identifier indicating that the processing is an illegal processing, and a microinstruction address of the second step when the microinstruction processing requires two or more steps in correspondence with the addresses designated by the OP codes of the user instructions used for designation of said first control memory; means for reading out a microinstruction from said first control memory and for reading out a corresponding identifier or a microinstruction address from said second control memory in response to said OP codes; and means for rendering said identifier or said microinstruction address stored in said second control memory effective or non-effective in response to an external setting signal.
Claim 13
Dependent Claim
190 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit'of a very large scale integrated semiconductor element; a first control memory in which are stored a plurality of microprograms consisting of a plurality of microinstructions connected externally to said arithmetic control unit for controlling it; a second control memory which is disposed inside said arithmetic control unit and in which is stored one of an identifier indicating that microinstruction processing may be completed in one step, an identifier indicating that the processing is an illegal processing, and a microinstruction address of the second step when the microinstruction processing requires two or more steps in correspondence with the addresses designated by the OP codes of the user instructions used for designation of said first control memory; means for reading out a microinstruction from said first control memory and for reading out a corresponding identifier or a microinstruction address from said second control memory in response to said OP codes; and means for rendering said identifier or said microinstruction address stored in said second control memory effective or non-effective in response to an external setting signal.
Claim 14
Dependent Claim
31 words
A system according to claim 11 characterized in that said external setting signal and the microinstruction read out from said first control memory are simultaneously received by said arithmetic control unit.
Claim 15
Dependent Claim
32 words
A system according to claim 12, characterized in that said microinstruction read out from said first control memory and said setting signal are simultaneously received by said arithmetic control unit during initialization.
Claim 16
Dependent Claim
124 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit of a very large scale integrated semiconductor element; a memory address register disposed inside said arithmetic control unit in which the memory address is set; a memory control register disposed inside said arithmetic control unit in which the memory control information is set; a memory address line and a memory data line connected to a common bus of said arithmetic control unit; a main memory connected to said memory address line and said memory data line; and means for simultaneously outputting a memory address from said memory address register and memory control information from said memory control register when said arithmetic control unit is accessing said main memory.
Claim 17
Dependent Claim
124 words
An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1-chip arithmetic control unit of a very large scale integrated semiconductor element; a memory address register disposed inside said arithmetic control unit in which the memory address is set; a memory control register disposed inside said arithmetic control unit in which the memory control information is set; a memory address line and a memory data line connected to a common bus of said arithmetic control unit; a main memory connected to said memory address line and said memory data line; and means for simultaneously outputting a memory address from said memory address register and memory control information from said memory control register when said arithmetic control unit is accessing said main memory.
Claim 18
Dependent Claim
31 words
A system according to claim 14, characterized in that a memory address latch circuit and a memory control latch circuit are interposed between said common bus and said memory address line.
Claim 19
Dependent Claim
61 words
A system according to claim 15, characterized in that memory address information and memory control information transferred from said common bus are latched in said memory address latch circuit and said memory control latch circuit at a timing at which a signal indicating that the information of said common bus is a memory address is output from said arithmetic control unit.
Claim 20
Dependent Claim
116 words
17 . An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1 - chip arithmetic control unit of a very large scale integrated semiconductor element; a common bus through which are time-divisionally transferred a plurality of kinds of data with different phases, between an external control memory and a main memory; means for collecting external status signals particular to each phase of said data transfer into a common signal line for supplying them to a particular terminal of said arithmetic control unit in synchronism with said phases; and means for latching said external status signals supplied to said particular terminal in a latch'circuit of said arithmetic control unit in synchronism with said phases.
Claim 21
Dependent Claim
116 words
17 . An information processing system incorporating a 1-chip arithmetic control unit comprising: a 1 - chip arithmetic control unit of a very large scale integrated semiconductor element; a common bus through which are time-divisionally transferred a plurality of kinds of data with different phases, between an external control memory and a main memory; means for collecting external status signals particular to each phase of said data transfer into a common signal line for supplying them to a particular terminal of said arithmetic control unit in synchronism with said phases; and means for latching said external status signals supplied to said particular terminal in a latch'circuit of said arithmetic control unit in synchronism with said phases.
References Cited (Backward Citations)
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