Patent EP0035326A2 successfully refreshed from Google Patents.
EP0035326A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Decoder circuit
Assignee: Fujitsu Ltd
•
Filing: 1981-02-05
•
Granted: —
•
Expires: 2001-02-05
Abstract
Abstract The decoder circuit receives address signals A o to A3 and selects one of 4x4 (= 16 ) word lines W 1 to W 16 for driving a semiconductor memory device for example. The decoder circuit has a high level selection circuit HS which receives upper address signals A o and A 1 and produces four outputs E 1 to E 4 , one of which is of a high level, while others are of a low level; and a low level selection circuit LS which receives lower address signals A 2 and A3 and produces four outputs F 1 to F 4 , one of which is of low level, while the others are of high level; and 4x4 (=16) coupling circuits CP 1 to CP 16 each of which corresponds to one of the word lines and each of which receives one output from the high level selection circuit HS and one output from the low level selection circuit LS. Each coupling circuit CP 1 to CP 16 selects a corresponding word line W 1 to W 16 only when the outputs of the high level selection circuit and the low level selection circuit which it is connected to receive are respectively and simultaneously high level and low level.
Inventors
- 👤 Hideaki Isogai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:40
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/001; H03M7/005; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; G11C8/00; G11C8/10; G11C8/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
238 words
A decoder circuit, for receiving a plurality of address signals and for selecting one of n x m lines in dependence upon the values of the address signals, including a high level selection circuit, for receiving some of the address signals of the plurality, having n outputs and operable to set one of the n outputs at high level, for specifying one of n line groups (which one depending upon the values of the address signals received by the high level selection circuit), and to provide (n-1) low level outputs in respect of the others of the n line groups, a low level selection circuit, for receiving the rest of the address signals of the plurality, having m outputs and operable to set one of the m outputs at low level, for specifying one of m line groups (which one depending upon the values of the address signals received by the low level selection circuit), and to provide (m-1) high level outputs in respect of the others of the m line groups, and n x m coupling circuits, corresponding respectively to the n x m lines, each connected to one output of the high level selection circuit and one output of the low level selection circuit and adapted to select the corresponding line when the high level selection circuit output and the low level selection circuit output connected thereto are respectively and simultaneously high level and low level.
Claim 2
Dependent Claim
238 words
A decoder circuit, for receiving a plurality of address signals and for selecting one of n x m lines in dependence upon the values of the address signals, including a high level selection circuit, for receiving some of the address signals of the plurality, having n outputs and operable to set one of the n outputs at high level, for specifying one of n line groups (which one depending upon the values of the address signals received by the high level selection circuit), and to provide (n-1) low level outputs in respect of the others of the n line groups, a low level selection circuit, for receiving the rest of the address signals of the plurality, having m outputs and operable to set one of the m outputs at low level, for specifying one of m line groups (which one depending upon the values of the address signals received by the low level selection circuit), and to provide (m-1) high level outputs in respect of the others of the m line groups, and n x m coupling circuits, corresponding respectively to the n x m lines, each connected to one output of the high level selection circuit and one output of the low level selection circuit and adapted to select the corresponding line when the high level selection circuit output and the low level selection circuit output connected thereto are respectively and simultaneously high level and low level.
Claim 3
Dependent Claim
65 words
A decoder circuit as claimed in claim 1, wherein each of the coupling circuits comprises a pnp transistor having an emitter connected to one of the outputs of the high level selection circuit, having a base connected, to one of outputs of the low level selection circuit, and having a collector connected to one of n x m line drivers provided for driving respective lines.
Claim 4
Dependent Claim
27 words
A decoder circuit as claimed in claim 2, wherein the collectors of all the pnp transistors are connected through resistors, respectively, to a single reference voltage source.
Claim 5
Dependent Claim
41 words
A decoder circuit as claimed in any preceding claim, wherein the low level selection circuit comprises a plurality of current switches connected in a series gate type arrangement for providing the one Ipw level output and the (m-1) high level outputs.
Claim 6
Dependent Claim
83 words
A decoder circuit as claimed in claim 4, wherein each of the current switches comprises a pair of npn transistors, the emitters of the transistors of each pair being connected to one another, the base of one transistor of each pair being arranged for receiving one of the address signals, the base of the other transistor of the pair being arranged for receiving a reference voltage, and wherein the outputs of the low level selection circuit are supplied from collectors of npn transistors.
Claim 7
Dependent Claim
30 words
A decoder circuit as claimed in claim 4 or 5, wherein the low level selection circuit further comprises a single constant current source for driving the plurality of current switches.
Claim 8
Dependent Claim
62 words
A decoder circuit as claimed in any preceding claim, wherein the high level selection circuit comprises a plurality of AND gates, each having two inputs for receiving signals derived from address signals received by the high level selection circuit, and having an output from which a high level is delivered only when the signals received at the two inputs are high level.
Claim 9
Dependent Claim
66 words
A decoder circuit as claimed in any one of claims 1 to 6, wherein the high level selection circuit comprises a plurality of NOR gates, each having two inputs for receiving signals derived from address signals received by the high level selection circuit, and having an output from which a high level is delivered only when the signals received at the two inputs are low level.
Claim 10
Dependent Claim
23 words
A decoder circuit as claimed in any preceding claim, wherein the n x m lines are word lines of- a semiconductor memory device.
Claim 11
Dependent Claim
13 words
A semiconductor memory device including a decoder circuit as claimed in claim 9.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.