Patent EP0033495A2 successfully refreshed from Google Patents.
EP0033495A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process for fabricating a high speed bipolar transistor
Assignee: International Business Machines Corp
•
Filing: 1981-01-23
•
Granted: —
•
Expires: 2001-01-23
Abstract
Abstract The process includes the steps of filling an emitter window (30) in an insulating layer on a semiconductor substrate with amorphous or polycrystalline silicon (33) of controlled thickness, implanting into silicon (33) ions producing a conductivity type opposite to that of substrate region (28) underneath window (30), where the conditions of depositing silicon (33) and the ion implantation are such that after the implantation the interface of silicon (33) and the substrate is amorphous, driving in the dopant while oxidizing the surface of silicon (33), stripping oxide coating (34) from silicon (33), depositing Pt on silicon (33) and reacting Pt with the rest of silicon (33) to form PtSi (38). With silicon (33) as diffusion source the diffusion into substrate region (28) extends to about the same distance in the horizontal as in the vertical direction. This ensures a sufficient horizontal displacement of the junction under the passivating layer to prevent a poorly passivated or shorted emitter base junction.
Inventors
- 👤 Cheng Tzong Horng
- 👤 Alwin Earl Michel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 05:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D10/00; H10D10/01; H10D10/051; H10D62/00; H10D62/40; H10D62/80; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92; Y10T; Y10T29/00; Y10T29/53; Y10T29/53909; Y10T29/53943
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
150 words
Process for fabricating a high speed bipolar transistor in a semiconductor substrate characterized in that an emitter window (30) is formed in an insulating layer deposited on that semiconductor substrate, that window (30) is filled with silicon (33), that ions are implanted into silicon (33), which produce a conductivity type opposite to that of substrate region (28) underneath window (30), where the conditions of depositing silicon (33) and the ion implantation are determined in such a way that after the implantation the interface of silicon (33) and the substrate is amorphous, that the surface of silicon (33) is oxidized and the dopant is concurrently driven in to form a shallow emitter, that the oxide coating (34) is stripped from silicon (33),- that Pt is deposited on silicon (33) and that the Pt is made to react with silicon (33), where silicon (33) is consumed completely with PtSi (38) being formed.
Claim 2
Dependent Claim
150 words
Process for fabricating a high speed bipolar transistor in a semiconductor substrate characterized in that an emitter window (30) is formed in an insulating layer deposited on that semiconductor substrate, that window (30) is filled with silicon (33), that ions are implanted into silicon (33), which produce a conductivity type opposite to that of substrate region (28) underneath window (30), where the conditions of depositing silicon (33) and the ion implantation are determined in such a way that after the implantation the interface of silicon (33) and the substrate is amorphous, that the surface of silicon (33) is oxidized and the dopant is concurrently driven in to form a shallow emitter, that the oxide coating (34) is stripped from silicon (33),- that Pt is deposited on silicon (33) and that the Pt is made to react with silicon (33), where silicon (33) is consumed completely with PtSi (38) being formed.
Claim 3
Dependent Claim
13 words
Process according to claim 1, wherein the implanted ion produce an n-type conductivity.
Claim 4
Dependent Claim
38 words
Process according to claim 1 or 2, wherein silicon (33) is made amorphous or polycrystalline, where in the latter case the ion implanting energy is made sufficient to render amorphous the interface of polycrystalline (33) and the substrate.
Claim 5
Dependent Claim
28 words
Process according to claim 3, wherein a sputtering technique is employed to deposit amorphous silicon (33) and a CVD process to deposit polysilicon (33) in emitter window (30).
Claim 6
Dependent Claim
185 words
Process according to any one of claims 1 to 4, wherein a base region (28) of the one conductivity is formed in a planar surface of a semiconductor substrate or a semiconductor layer (16) of the other conductivity, a blanket layer of an insulating material is deposited on the semiconductor surface, an emitter window (30) is formed in the area of the insulating layer overlying base region (28), a blanket layer of silicon (33) is deposited on the structure, ions are implanted producing a conductivity opposite to that of base region (28), the surface of silicon (33) is oxidized and concurrently the dopant is driven into the area of region (28) being in contact with silicon (33) to form a shallow emitter region (35), oxide (34) is selectively removed preserving oxide (34) at least over emitter window (30), silicon (33) is selectively removed using oxide (34) as etch mask, oxide (34) is completely removed followed by a blanket deposition of Pt, the structure is heated to react Pt with the underlying silicon (33) to form PtSi and the Pt not transformed to PtSi is stripped.
Claim 7
Dependent Claim
17 words
Process according to claim 5, wherein base region (28) is doped with a dopant producing p-type conductivity.
Claim 8
Dependent Claim
93 words
Process according to any one of claims 1 to 4 and 6, wherein the filling of emitter window (30) with silicon (33) is accomplished by depositing a layer (41) of CVD Si0 2 on the blanket insulating layer, by forming emitter window (30) in layer (41) and in the insulating layer, by depositing a blanket layer of silicon (33) and on top of blanket layer (42) a photoresist by forming a planar surface by thinning the structure, i.e. layer (42) and silicon (33) homogeneously until silicon (33) is completely removed outside window (30).
Claim 9
Dependent Claim
29 words
Process according to any one of claims 1, 3 to 5 and 7 wherein the base region is doped with an n-dopant and the emitter region with a p-dopant.
Claim 10
Dependent Claim
25 words
Process according to any one of claims 1 to 8, wherein a composite layer of insulating material consisting of at least two materials is used.
Claim 11
Dependent Claim
54 words
Process according to claim 9, wherein the insulating layer is made of a first material (29) and a second material (17), and emitter window (30) is formed in such a manner that the second material (17) is adjacent said planar surface of the substrate and may undercut a portion of said first material (29).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.