Microprogram controlled data processor

Claim 2

A data processor controlled by microprograms comprising an instruction register in which is set a machine instruction having a suboperation code, in addition to an operation code, and a control memory which stores micro instructions, characterized in that the data processor further comprises a micro instruction register which temprorarily memorizes a micro instruction read out from said control memory, by using the operation code of the machine instruction set in the instruction register, and suboperation index codes contained in a micro instruction read out from the control memory by using the suboperation code of said machine instruction, a selector and a means for logical operation, each of said micro instructions which are stored in the control memory and read out by using said operation code having a next address field and an address control field, said selector selecting one of said suboperation index codes according to the content of said address control field, the next access to said control memory being performed by using a next address data obtained by the logical operation between the content data of said next address field and the selected suboperation index code by using said means for logical operation.

Claim 3

A data processor as set forth in claim 1, wherein said data processor further comprises a base address register, which temporarily memorizes the content of said next address field of a micro instruction read out to said micro instruction register, and a suboperation latch, which temporarily memorizes the content of said address control field of said micro instruction, the content of the next address field and the content of the address control field of the micro instruction read out from said control memory to the micro instruction register by using said operation code being stored in said base address register and said suboperation latch, respectively, thereafter said micro instruction which contains said suboperation index codes being read out from said control memory by using said suboperation code, said selector selecting one of suboperation'index codes according to the content of said suboperation latch, the next access to said control memory being performed by using a next address data obtained by the logical operation between the content data of said next address field stored in said base address register and the selected suboperation index code by using said means for logical operation.

Claim 4

A data processor as set forth in claim 1 or 2, wherein said logical operation is an addition.

Claim 5

A data processor as set forth in claim 1 or 2, wherein said logical operation is a logical combination in which said next address data is obtained by using the content data of said next address field as upper bits and by using said selected suboperation index code as lower bits.

Claim 6

A data processor controlled by microprograms comprising an instruction register in which a machine instruction, having a suboperation code in addition to an operation code, is set and a control memory, which stores micro instructions, characterized in that the data processor further comprises a micro instruction register which t emporarily memorizes a micro.instruction read out from said control memory by using said operation code, a second control memory storing a plurality of suboperation index codes which are read out by using said suboperation code, a suboperation index register in which an output from said second control memory is set, a selector and a means for logical operation, each of said micro instructions which are stored in said control memory and read out by using said operation code having a next address field and an address control field, said selector selecting one of said suboperation index codes set in said suboperation index register according to the content of said address control field of said micro instruction read out to said micro instruction register, the next access to said memory being performed by using a next address data obtained by the logical operation between the content data of said next address field and the selected suboperation index code by using said means for logical operation.

Claim 7

A data processor controlled by microprograms comprising an instruction register in which a machine instruction, having a suboperation code in addition to an operation code, is set and a control memory, which stores micro instructions, characterized in that the data processor further comprises a micro instruction register which t emporarily memorizes a micro.instruction read out from said control memory by using said operation code, a second control memory storing a plurality of suboperation index codes which are read out by using said suboperation code, a suboperation index register in which an output from said second control memory is set, a selector and a means for logical operation, each of said micro instructions which are stored in said control memory and read out by using said operation code having a next address field and an address control field, said selector selecting one of said suboperation index codes set in said suboperation index register according to the content of said address control field of said micro instruction read out to said micro instruction register, the next access to said memory being performed by using a next address data obtained by the logical operation between the content data of said next address field and the selected suboperation index code by using said means for logical operation.

Claim 8

A data processor as set forth in claim 5, wherein said logical operation is an addition.

Claim 9

A data processor as set forth in claim 5, wherein said logical operation is a logical combination in which said next address data is obtained by using the content data of said next address field as upper bits and by using said selected suboperation index code as lower bits.