Patent EP0032279A1 successfully refreshed from Google Patents.
EP0032279A1
Expired / Lapsed
EP
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One transistor-one capacitor memory cell
Assignee: CTU of Delaware Inc
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Filing: 1980-01-11
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Granted: —
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Expires: 2000-01-11
Abstract
Abstract An integrated circuit memory cell pair having its data lines (30) (32) (34) insulated with respect to the semiconductor substrate (70)at all points other than the point of electrical contact (62) to the transistors of each memory cell. The semiconductor substrate has drain and source regions (12) (18) (22) (28) about the transmission channel of the field effect transistor and has a first capacitor electrode integral with one terminal of the transistor. A first polysilicon layer (82) insulatively disposed relative to the substrate provides a conductive layer for a second capacitor electrode for each memory cell. A second insulatively disposed polysilicon layer (86) provides the gate regions (16) (26) of the transistors and the data lines. The data lines make electrical contact through a self-aligned embedded contact. Using this construction, a highly dense memory cell array is achieved without sacrificing capacitor area.
Inventors
- 👤 Tsiu Chiu Chan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 08:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/813; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
304 words
L In an integrated circuit memory formed in a semiconductor substrate having a multiplicity of memory cell pairs, each memory cell pair being coupled to one of a plurality of word select lines of said memory and each memory cell pair being coupled to two of a plurality of data lines of said memory, the improvement in each of said memory cell pairs which comprises: a first region including a first transmission channel disposed in said semiconductor substrate of said memory cell pair; a first data line electrically coupled to the first region and insulatively disposed from said semiconductor substrate except at the point of electrical coupling; , a second region including a second transmission channel disposed in said semiconductor substrate of said memory cell pair; a second data line electrically coupled to said second region and insulatively disposed from said semiconductor substrate except at the point of electrical coupling; conductive gate means for controlling electrical current flowing in said first and second transmission channels, said gate means being insulatively disposed with respect to the first and second transmission channels in said first and second regions, respectively, said gate means having an electrical contact rerion for connection to a word select line, said first transmission channel constituting a portion of and being electrically coupled to said first region, and said second transmission channel constituting a portion of and being electrically coupled to said second region; and, conductive capacitive means insulatively disposed with respect to said first and second regions, respectively, said conductive capacitive means defining first and second capacitor regions operable for storing electrical charge, said first capacitor region constituting a portion of said first region and electrically coupled to said first transmission channel, and said second capacitor region constituting a portion of said second region and electrically coupled to said second transmission channel
Claim 2
Dependent Claim
25 words
The integrated circuit memory as set forth in Claim 1 wherein said first and second capacitor regions are diffusion regions disposed in said semiconductor substrate.
Claim 3
Dependent Claim
59 words
The integrated circuit memory as set forth in any preceding Claim wherein said conductive capacitive means is a continuous layer over at least a section of tαe integrated circuit memory and exposed at said first and second transmission channels and at points of electrical coupling of said first and second data lines and said first and second regions, respectively.
Claim 4
Dependent Claim
50 words
The integrated circuit memory as set forth in any preceding Claim wherein said first and seqond data lines are electrically isolated from said semiconductor substrate at all points other than at the points of electrical coupling of said first and second data lines and said first and second regions, respectively.
Claim 5
Dependent Claim
49 words
The integrated circuit memory as set forth in any preceding Claim wherein said conductive capacitive means is electrically isolated from and disposed between said semiconductor substrate and said first and second data lines, whereby electrical signals in the first and second data lines are decoupled from said semiconductor substrate.
Claim 6
Dependent Claim
42 words
The integrated circuit memory as set forth in any preceding Claim wherein each point of electrical coupling of said first and second data lines and said first and second regions, respectively, is an embedded contact, self-aligned to said first and second regions.
Claim 7
Dependent Claim
21 words
The integrated circuit memory as set forth in any preceding Claim wherein said semiconductor substrate is of P-type doped monocrystalline semiconductor.
References Cited (Backward Citations)
No citation records indexed.
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