Digital indication type speedometer

Claim 2

A digital indication type speedometer comprising: a speed counter for counting speed pulses emitted in proportion to a vehicle speed for a given gate time; an indication register for latching a value to be indicated commensurate to an output from said speed counter; an indicator for indicating the value latched in said indication register; and a hysteresis processing circuit for rewriting the value latched in said indication register in accordance with an output of said speed counter only when a difference between the output of said speed counter and the value latched in said indication register is not within tolerance limit upon comparison therebetween.

Claim 3

A digital indication type speedometer as set forth in claim 1, wherein said tolerance limit in said hysteresis processing circuit has identical reference values with each other in either positive or negative direction.

Claim 4

A digital indication type speedometer as set forth in claim 2, wherein said identical reference value are ± 1 km/h or ± 1 mile/h.

Claim 5

A digital indication type speedometer as set forth in claim 2, wherein said hysteresis processing circuit comprises: a digital subtraction circuit for calculating a difference between the output of said speed counter and the value latched in said indication register; a digital reference circuit for digitally presetting a hysteresis reference value; . a code-converting circuit for code-converting the digital reference value of said digital reference circuit into a value of complement thereof; a first comparison circuit for emitting an output based on the result of subtraction of said digital subtraction circuit when the output from said speed counter, exceeding the reference value of said digital reference circuit, becomes larger than the value latched in said indication register; a second comparison circuit for emitting an output based on the result of subtraction of said digital subtraction circuit when the output from said speed counter, exceeding the reference value of said digital reference circuit, which . has been code-converted into a value of complement thereof by said code-converting circuit, becomes smaller than the value latched in said indication register; a first AND gate openable by a positive sign of the result of subtraction of said digital subtraction circuit, so as to pass an output from said first comparison circuit; a second AND gate openable by a negative sign of the result of subtraction of said digital subtraction circuit, so as to pass an output from said second comparison circuit; and an OR gate for emitting a logical sum of said first and second AND gates as a difference signal.

Claim 6

A digital indication type speedometer as set forth in claim 2, wherein said hysteresis processing circuit comprises: a digital subtraction circuit for calculating a difference between the output of; said speed counter and the value latched in said indication register; a digital/analog converser for converting an output as the result of subtraction in said digital subtraction circuit into an analog signal; an absolute value circuit for obtaining an absolute value of an output from said digital/analog converter; an analog reference circuit for analogously presetting a hysteresis reference value; and a comparison circuit for comparing an output from said absolute value circuit with the reference value in said analog reference circuit and emitting a difference signal.

Claim 7

A digital indication type speedometer as set forth in claim 1, wherein said tolerance limit in said hysteresis processing circuit has different reference values with each other between positive side and negative side.

Claim 8

A digital indication type speedometer as set forth in claim 6, wherein said hysteresis processing circuit comprises: a digital subtraction circuit for calculating a difference between the output of said speed counter and the value latched in said indication register; a first digital reference circuit for digitally presetting a positive hysteresis reference value; a first comparison circuit for emitting an output based on an output of the result of subtraction of said digital subtraction circuit when the output from said speed counter, exceeding the positive reference value, becomes larger than the value latched in said indication register; a second digital reference circuit for dismally presetting a negative hysteresis reference value; a second comparison circuit for emitting an output based on an output of the result of subtraction of said digital subtraction circuit when the output from said speed counter, exceeding the negative reference value, becomes smaller than the value latched in said indication register; and an OR gate for emitting a logical sum of outputs from said first and second comparison circuits as a difference signal.

Claim 9

A digital indication type speedometer as set forth in claim 6, wherein said hysteresis processing circuit comprises: a digital subtraction circuit for calculating a difference between the output of said speed counter and the value latched in said indication register; a digital/analog converter for converting an output as the result of subtraction in said digital subtraction circuit into an analog signal; a first analog reference circuit for analogously presetting a positive hysteresis reference value; a first comparison circuit for comparing the positive reference value with an output from said digital/analog converter and emitting an output when the output from said digital/analog converter is larger than the positive reference value; a second analog reference circuit for analogously presetting a negative hysteresis reference value; a second comparison circuit for comparing the negative reference value with an output from said digital/analog converter and emitting an output when the output from said digital/analog converter is than the negative reference value; and an OR gate for emitting a logical sum of outputs from said first and second comparison circuit as a difference signal.

Claim 10

A digital indication type speedometer as set forth in claim 1, further comprising: a zero indication discriminating circuit for emitting a zero indication signal to rewrite the value latched in said indication register and indicate zero in response to the output from said speed counter when the output from said speed counter is zero.

Claim 11

A digital indication type speedometer as set forth in claim 1, further comprising: a zero indication discriminating circuit for emitting a zero indication signal to rewrite the value latched in said indication register and indicate zero in response to the output from said speed counter when the output from said speed counter reaches a predetermined value or less.