Patent EP0031638A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0031638A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

A logic circuit

Assignee: Fujitsu Ltd
•
Filing: 1980-11-06
•
Granted: —
•
Expires: 2000-11-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The logic circuit has cascade-connected flip-flops A, B, C and D. The data inputs D A , Da, Dc and D D to the flip-flops have gate arrangements G A , G B , Gc and G D connected to them. The circuit receives either a shift signal SHT or a count signal CNT. When the shift signal SHT is received the gate arrangements function so that serial input data Sin is fed through and to the flip-flops A, B, C and D in the manner of a shift register. When the count signal CNT is received the gate arrangements function so that the flip-flops A, B, C, D behave as a counter. The same flip-flops A, B, C, D serve for serial-to- parallel conversion of serial input data Sin, counting and parallel-to-serial conversion of a count result.

Inventors

  • 👤 Takanori Sugihara
  • 👤 Makoto Yoshida

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 10:55
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/54; G; G11; G11C; G11C19/00

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 83 words
A logical circuit having a plurality of cascade-connected flip-flops, each flip-flop having connected to an input part thereof a logical gate group, characterised in that the logical gate group of each flip-flop comprises gates arranged to be opened and closed by a shift signal and by a count signal, and in that the logical gate groups are arranged so that the flip-flops serve alternatively to provide a shift register and a counter, in response to the shift signal and the count signal respectively.
Claim 2
Dependent Claim 83 words
A logical circuit having a plurality of cascade-connected flip-flops, each flip-flop having connected to an input part thereof a logical gate group, characterised in that the logical gate group of each flip-flop comprises gates arranged to be opened and closed by a shift signal and by a count signal, and in that the logical gate groups are arranged so that the flip-flops serve alternatively to provide a shift register and a counter, in response to the shift signal and the count signal respectively.
Claim 3
Dependent Claim 149 words
A logical circuit according to claim 1, wherein the logical gate group connected to an nth (n = 1, 2, 3, ...) flip-flop has a construction which embodies the following expression, or the inverse of the following expression, or logical equivalents thereof, where D is data to be input to the nth flip-flop and is the data output from the logical gate group connected to the nth flip-flop; SHT is the shift signal; CNT is the count signal and bears a relationship to the shift signal such that CNT = SHT; Q is the Q output from the nth flip-flop; Q is the Q output from the nth flip-flop; Q (n-1) is the Q output from the (n-1)th flip -flop, which is serial input data Sin in the case of the logical gate group connected to the first flip-flop; and CRY = Q 1 ·Q 2 ····Q (n-1) Ú
Claim 4
Dependent Claim 40 words
A logical circuit according to claim 2, wherein the logical gate group connected to the nth flip-flop has a construction which embodies the simplified expression as follows, or the inverse of the simplified expression as followsü or logical equivalents thereof,
Claim 7
Dependent Claim 16 words
A logical circuit according to any preceding claim, wherein the flip-flops are D-type or delay flip-flops.
Claim 8
Dependent Claim 16 words
A logical circuit according to claim 1, 2 or 3, wherein the flip-flops are J-K flip-flops.
Claim 9
Dependent Claim 18 words
A logical circuit according to any preceding claim, wherein the gate groups employ AND gates and OR gates.
Claim 10
Dependent Claim 22 words
A logical circuit according to claim 1, 2, 3, 4 or 5, wherein the gate groups employ NAND gates and AND gates.
Claim 11
Dependent Claim 21 words
A logical circuit according to claim 1, 2, 3,4 or 5, wherein the gate groups employ AND gates and NOR gates.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag