Patent EP0031490A2 successfully refreshed from Google Patents.
EP0031490A2
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EP
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One device field effect transistor AC stable random access memory array
Assignee: International Business Machines Corp
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Filing: 1980-12-04
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Granted: —
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Expires: 2000-12-04
Abstract
Abstract Disclosed is an integrated circuit electronic memory array having a plurality of FET memory cells (T, C) arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell (T, C) of the array has a capacitive storage region (C), an adjacent channel region, and a gate region (G) for controlling the transfer or binary information through the channel region in and out of the capacitive storage region (C). Each memory cell (T, C) also has a bit line (BL) contact region which is shared with an adjacent memory cell. The word lines (WL) are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region (C) of a first one of the memory cells (T, C) and electrically integral with the gate region (G) of a second one of the memory cells (T, C). The column arrangement of memory cells (T, C) is interdigitated such that the memory cells associated with a single bit line (BL) are arranged in first and second parallel lines (A, B) along both the left and right sides of each bit line (B, L). Thus, the bit line (BL) is arranged in a zig-zag configuration alternately contacting memory cells (T, C) arranged along its left and right side.
Inventors
- 👤 Roy Edwin Scheuerlein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 04:30
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
146 words
An integrated circuit electronic memory array having a plurality of memory cells (T, C), each memory cell of said array having a gate region (G) for controlling the transfer of binary information in and out of a corresponding storage region (C), and a bit line contact region (N) characterized by a plurality of word lines (WL) arranged in rows each of said word lines (WL) alternately passing over the storage region (C) of a first one of said memory cells (T, C) and being electrically integral with the gate region (G) of a second one of said memory cells; and memory cells (T, C) being arranged along first and second parallel lines (A, B) in each one columns, and a plurality of bit lines (BL) having portions extending to electrically contact memory cells (T, C) arranged along said first and second parallel lines (A, B), respectively.
Claim 2
Dependent Claim
146 words
An integrated circuit electronic memory array having a plurality of memory cells (T, C), each memory cell of said array having a gate region (G) for controlling the transfer of binary information in and out of a corresponding storage region (C), and a bit line contact region (N) characterized by a plurality of word lines (WL) arranged in rows each of said word lines (WL) alternately passing over the storage region (C) of a first one of said memory cells (T, C) and being electrically integral with the gate region (G) of a second one of said memory cells; and memory cells (T, C) being arranged along first and second parallel lines (A, B) in each one columns, and a plurality of bit lines (BL) having portions extending to electrically contact memory cells (T, C) arranged along said first and second parallel lines (A, B), respectively.
Claim 3
Dependent Claim
54 words
The integrated memory array of Claim 1, characterized in that each said bit line contact region is a common bit line contact region for a pair of adjacent memory cells along said plurality of bit line (BL), so that the bit line (BL) has zig-zag fashion traversing its centerline (C) from left to right.
Claim 4
Dependent Claim
33 words
An integrated memory array of Claim 1, characterized in that at least one of said plurality of word lines (WL) is spaced substantially the same distance from each of its adjacent word lines.
Claim 5
Dependent Claim
31 words
An integrated memory array of Claims 1 to 3, characterized in that each said plurality of bit lines (BL) is formed substantially passing over each said plurality of word lines (WL).
Claim 6
Dependent Claim
46 words
An integrated memory array of Claim 4, characterized in that each said plurality of word lines (WL) is formed from a conductive material selected from the group consisting of polysilicon and polysilicide material, and each said plurality of bit lines (BL) is formed from a metal.
Claim 7
Dependent Claim
37 words
An integrated electronic memory of Claim 4, characterized in that each said plurality of word lines (WL) and bit lines (BL) is formed from a conductive material selected from the group consisting of polysilicon and polysilicide material.
Claim 8
Dependent Claim
155 words
An integrated electronic memory of Claim 1, characterized in that said plurality of memory cells (T, C) and associated support circuits are formed on a semiconductor substrate (10) doped with impurities of a first conductivity type and that a doped region (N) of a second conductivity type is introduced into said substrate (10) and forming a PN junction therewith, one of said plurality of bit lines (BL) contacting said doped region (N) and forming said bit line contact region therewith; and that a channel region is in said substrate (10) adjacent said doped region (N) and underlying the gate region (G) electrically integral with one of said plurality of word lines (WL); and that a capacitor region (C) is in said substrate (10) adjacent said channel region and underlying a plate region (PR), forming said corresponding storage region; and that an isolation region (17) is formed into said substrate (10) adjacent said capacitor region (C).
Claim 9
Dependent Claim
35 words
An integrated memory array of Claim 7, characterized in that said doped region (N) is shared with an adjacent memory cell also having a capacitor region (C), a channel region, and an isolation region (17).
Claim 10
Dependent Claim
30 words
An integrated memory array of.Claim 7, characterized in that said first conductivity type is formed by P type impurities and said second conductivity type is formed by N type impurities.
Claim 11
Dependent Claim
21 words
An integrated circuit memory array of Claim 7, characterized in that said word line (WL) is formed from a polysilicon material.
Claim 12
Dependent Claim
21 words
An integrated circuit memory array of Claim 7, characterized in that said word line (WL) is formed from a polysilicide material.
Claim 13
Dependent Claim
36 words
An integrated circuit memory array of Claim 7, characterized in that said word lines (WL) are positioned entirely above the substrate surface and said bit lines (BL) are positioned substantially passing over said word lines (WL).
Claim 14
Dependent Claim
18 words
An integrated circuit of Claim 12, characterized in that said bit lines (BL) are formed from a metal.
Claim 15
Dependent Claim
103 words
An integrated memory array of Claims 1 - 13, characterized in that a plurality of word lines (WL) are arranged in rows, each said word lines alternately passing over the storage region (C) of a first one of said memory cells (T, C) and being electrically integral with the gate region (G) of a second one of said memory cells; and that a plurality of bit lines (BL) are arranged in columns substantially along parallel center lines orthogonal to said word lines (WL), each said plurality of bit lines alternately contacting a bit line contact region on opposite sides of its center line.
Claim 16
Dependent Claim
37 words
An integrated memory array of Claim 14, characterized in that each said bit line contact region is a common bit line contact region for a pair of adjacent memory cells along said plurality of bit lines (BL).
Claim 17
Dependent Claim
34 words
An integrated memory array of Claim 14, characterized in that at least one of said plurality of word lines (WL) is spaced substantially the same distance from each of its adjacent word lines (WL).
Claim 18
Dependent Claim
29 words
An integrated memory array of Claim 14, characterized in that each said plurality of bit lines (BL) is formed substantially passing over each said plurality of word lines (WL).
Claim 19
Dependent Claim
46 words
An integrated memory array of Claim 14, characterized in that each said plurality of word lines (WL) is formed from a conductive material selected from the group consisting of polysilicon and polysilicide material, and each said plurality of bit lines (BL) is formed from a metal.
Claim 20
Dependent Claim
33 words
An integrated memory array of Claim 14, characterized in that each said plurality of word lines (WL) is formed from a conductive material selected from the group consisting of polysilicon and polysilicide material.
Claim 21
Dependent Claim
144 words
An integrated memory array of Claim 14, characterized in that said plurality of memory cells and associated support circuits are formed on a semiconductor substrate (10) doped with impurities of a first conductivity type, characterized by a doped region (N) of a second conductivity type introduced into said substrate (10) and forming a PN junction therewith, one of said plurality of bit lines (BL) contacting said doped region and forming said bit line contact region therewith; a channel region in said substrate (10) adjacent said doped region (N) and underlying the gate region (G) electrically integral with one of said plurality of word lines (WL); a capacitor region (C) in said substrate (10) adjacent said channel region and underlying a plate region (PR), forming said corresponding storage region (C); and an isolation region (17) formed into said substrate (10) adjacent said capacitor region (C).
Claim 22
Dependent Claim
34 words
An integrated memory array of Claim 20, characterized in that said doped region (N) is shared with an adjacent memory cell also having a capacitor region, a channel region, and an isolation region (C).
Claim 23
Dependent Claim
31 words
An integrated memory array of Claim 20, characterized in that said first conductivity type is formed by P type impurities and said second conductivity type is formed by N type impurities.
Claim 24
Dependent Claim
20 words
An integrated memory array of Claim 20, characterized in that said word line (WL) is formed from a polysilicon material.
Claim 25
Dependent Claim
20 words
An integrated memory array of Claim 20, characterized in that said word line (WL) is formed from a polysilicide material.
Claim 26
Dependent Claim
33 words
An integrated memory array of Claim 20, characterized in that said word lines (WL) are positioned entirely above the substrate surface and said bit lines are positioned substantially passing over said word lines.
Claim 27
Dependent Claim
19 words
An integrated memory array of Claim 25, characterized in that said bit lines (BL) are formed from a metal.
Claim 28
Dependent Claim
42 words
An integrated memory array of Claims 1 - 7, characterized by an additional doped region of a second conductivity type also introduced into said substrate (10) and forming a PN junction therewith, and positioned between said channel region and said capacitor region.
Claim 29
Dependent Claim
42 words
An integrated memory array of Claims 1 - 8, characterized by an additional doped region of a second conductivity type also introduced into said substrate (10) and forming a PN junction therewith, and positioned between said channel region and said capacitor region.
References Cited (Backward Citations)
No citation records indexed.
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