Improvements in cardiac pacer

Claim 2

Appnratus for detecting a component of a cardiac signal comprising: sensing means for sensing a cardiac electrical signal; quantizer means receiving said cardiac electrical signal for generating a train of binary signals representative of the slope of said cardiac electrical signal; first detector means responsive to said binary signals for detecting whether said signals met first predetermined selection cirteria over a first portion of a cardiac cycle; second detector means responsive to said binary signals for detecting whether said signals met a second predetermined selection criteria over a second portion of the same cardiac cycle, said first and second portions of said cardiac cycle being separated in time; and coincidence detection means responsive to the outputs of said first and second detector means to define a valid detection when said outputs indicate said first and second criteria are met for the same cardiac cycle.

Claim 3

Implantable cardiac pacing apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; signal detector means including, sensing means responsive to a cardiac signal on said electrode means; filter means receiving the signal sensed by said sensing means for quantizing said sensed signal and continuously generating digital words representative of the slope of said sensed signal over a sample time window; parameter memory means for storing signals representative of predetermined selection criteria for defining at least one component of a cardiac cycle signal; , selection circuit means responsive to the quantized output signals of said filter means and said stored selection criteria signals for generating a detection signal if said digital slope words meet said predetermined selection criteria; and generator means for generating a stimulating signal and coupling the same to said electrode means if said selection circuit means does not generate said detection signal within a predetermined time from a previous detection signal or a previous stimulating signal.

Claim 4

Implantable cardiac pacing apparatus comprising: , electrode means adapted to couple a stimulating signal to the heart; sensing means for sensing signals on said electrode means; selection circuit means responsive to the signals sensed by said sensing mcnns for detecting a predetermined component of a natural cardiac cycle; first timing circuit means having a first timing source for generating timing signals representative of time periods in a cardiac cycle including a rate time out period during which said predetermined component is expected to occur; second timing circuit means synchronized with snid first timing circuit means and having a second timing source independent of said first timing source for generating n rate limit enable signal defining a predetermined minimum period relative to the commencement of a cardiac cycle and ending during a normal cardiac rate time out period; and generator means for generating a stimulating signal on said electrode means if said selection circuit means does not detect said predetermined component during said rate time out period and being inhibited from generating said stimulating signal until said rate limit signal is generated by said second timing circuit means.

Claim 6

. Cardiac pacing apparatus comprising; electrode means including at least a first electrode adapted to stimulate the heart; signal detector means responsive to cardiac signals on said electrode means for detecting a natural heartbeat and for generating a reset signal in response to the detection of either a natural cardiac signal or a stimulating cardiac signal; timing circuit means response to said signal detector means for generating timing period signals for each cardiac cycle including a refractory period signal defining a refractory period, and a Ventricular Rate Time Out signal defining a Ventriculnr Rate Time Out period following siiid refractory period signal; generator means responsive to said timing signals for generating a stimulating pulse on said electrode means at the end of said Ventricular Rate Time Out perod if a natural heartbeat has been detected by said detector means during such period; said detector means being responsive to said cardiac signals and said timing signals for detecting a premature ventricular contraction during a predetermined portion of said refractory period; and circuit means responsive to said detector means for reducing said Ventricular Rate Time Out period to a predetermined amount if a premature ventricular contraction is detected during said refractory period; said generator means being operative to generate said stimulating pulse if a natural heartbeat is not detected in said reduced Ventricular Rate Time Out period.

Claim 7

. In cardiac pacing apparatus, the combination comprising: first oscillator circuit means for generating a periodic signal at a first repetition rate; first divider circuit means responsive to the output signal of said first oscillator circuit means for generating a digital signal representative of lapsed time; first memory circuit means for storing selectively addressable digital words representative of sequentially occurring predetermined time marks relative to a commencement time; first address means for addressing said time mark words stored in said first memory circuit means; first comparator circuit means responsive to one of said time mark words from said first memory means selected by said first address means representative of a predetermined time in a cardiac cycle for comparing the same with the contents of said first divider circuit means representative of lapsed time in a cardiac cycle; said first digital comparator circuit means generating an output signal when said lapsed time signal contents of said first divider circuit means is equal to a time mark word addressed and selected from said first memory circuit means; said output signal being representative of the occurrence of a predetermined time in said cardiac cycle as represented by said digital time mark word stored in said first memory circuit means.

Claim 8

. In a cardiac siqnnl detection apparatus, the combination comprising: sensing means for sensing a cardiac signal, and including sample-data circuit means receiving said cardiac signal for quantizing the same; detector circuit means including programmable means having at least one detection parameter programmable and responsive to the signal of said sensing means for identifying a predetermined signal component of a cardiac signal; detection parameter control memory means for storing digital control words representative of different values of said parameter; data bus means including n plurality of sections, at least one section interconnecting said parameter control memory means with said detector circuit means for coupling said control words thereto; gate means responsive to an enable signal for communicating said bus sections together; write circuit means for storing a digital word representative of a desired word in said control memory inenns; address register means for selectively addressing a location in said control memory means; and state controller circuit means for generating an enable signal to said gate circuit means during a predetermined portion of a cardiac cycle for coupling said busses together to write said control data word in said write register into the addressed word of the selected memory and for disconnecting said busses thereafter, whereby said data bus means couples a selected parameter to said detection circuit means when said gate circuit means is disabled, and said bus sections are selectively placed in communication for writing data into said memory.

Claim 9

In cardiac pacing apparatus, including electrode means for stimulating the heart and for sensing a cardiac signal; detector circuit means responsive to the signal on snid electrode means for detecting a predetermined component of n ciirdinc signal in response thereto; timing circuit means responsive to the output of said detection circuit means for generating signals representative of a predetermined ventricular rate time out period during which a natural R wave is expected to occur in a normal cardiac cycle; pulse generator circuit means responsive said timing circuit means for generating a stimulating signal and for coupling the same said electrode means to stimulate the heart in the absence of a detected R wave during said ventricular rate timc out period; the improvement comprising: function circuit means for performing a predetermined function in said apparatus; status control memory means for storing control data signals representative of a desired status condition; and state controller means responsive to the contents of said status control memory means for selectively enabling or disabling the operation in functioning of said circuit means in response to the contents stored in an associated word in said status control memory circuit means.

Claim 10

Implantable cardiac pacing apparatus comprising: electrode means including at least a first electrode adapted to stimulate the heart; signal detector means including sensing means responsive to a cardiac signal on said electrode means; and digital filter circuit means receiving the signal sensed by said sensing means for quantizing said sensed signal and being programmable for identifying predetermined selection parameters of said signal; memory means for storing signals representative of predetermined selection criteria defined by said selection parameters for said signal including at least a first data word for identifying an R wave and A second data word for identifying a T wave; . selection circuit mcans responsive to the quantized output signals of said digital filter means and said stored selection parameter signals for generating a detection signal if said quantized signals of said digital filter means meet said predetermined selection criteria; timing circuit means for establishing timing signals representative of a cardiac cycle including a ventricular refractory period and a ventricular rate time out period; and state controller circuit means responsive to said timing signals for coupling said T wave selection criteria data word from said memory means to said digital filter means during said refractory period and for coupling said R wave selection criteria data words from said mcmory means to said digital filter means during said ventricular rate time out period.

Claim 11

Cardiac pacing apparatus comprising: sensing means including an electrode adapted to sense a cardiac signal; detector circuit means receiving said sensed cardiac signal for detecting a predetermined component of said signal and generating a signal defining the commencement of a cardiac cycle; timing circuit means responsive to said commencement signal for generating a timing signal representative of the end of a ventricular rate time out period; pulse gcncrntor means responsive to said timing signals for generating a stimulating pulse on said electrode means if said detector means has not detected a natural heartbeat with said ventricular rate time out period; the improvement comprising: first memory circuit means for storing a plurality of first data words, each defining n different duration for said ventricular rate time out period and storing a plurality of second data words, each defining a different time duration for said stimulating signal; circuit means responsive to the application of a predetermined external signal for generating an internal signal in said pacing apparatus representative thereof; status memory means including a first programmable status signal having an enable and a disable state; and temporary mode counter circuit means responsive to said internal signal, and said timing signals for counting a predetermined number of cardiac cycles and including control circuit responsive to said first status signal's being in an enable state means for selecting one of said first data words from said memory means to define a predetermined cardiac rate and one of said second data words to define the width of a stimulating pulse, said control circuit means of said temporary mode counter circuit means disabling operation of said apparatus at said programmed rate and pulse width after said counter temporary mode counter circuit means has counted n predetermined number of cardiac cycles.