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EP0031183A2
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Multi-processor computer system
Assignee: Koninklijke Philips NV
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Filing: 1980-12-09
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Granted: —
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Expires: 2000-12-09
Abstract
Abstract A multi-processor computer system is distributed over error-isolation areas, each of these areas containing a processor element (12, 14, 16 or 18), an encoder (20, 22, 24 or 26), a section (28, 30, 32 or 34) of a memory and an information-reconstruction section (54, 56, 58 or 60) which are connected in-this order in a cyclic path. The processor elements work in parallel on the same data-word, which has a certain length. When the result of the processing has to be stored in the memory, each encoder (20, 22, 24 or 26) forms a code-symbol of shorter length, on the basis of the data-word. The set of code-symbols formed on the basis of the data-word forms a code-word with a larger bit length than the data-word mentioned. By means of an error-correcting code at least one erroneous code-symbol in the code-word can be corrected. The code symbols are stored in the respective memory sections (28, 30, 32 or 34). If the data-word concerned has to be further processed, all corresponding code-symbols are fed to all information-reconstruction sections (54, 56, 58 or 60). Peripheral equipment (Figure 6b not shown) can be connected in the cyclic path, with implementation of distinctive levels of redundancy. (Figure 3).
Inventors
- 👤 Thijs Krol
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 19:15
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
318 words
A multi-processor computer system comprising a number n (n) 2) of processor elements operating in parallel (12, 14, 16, 18), each of which have a first data input and a first data output, which computer system further comprises a memory with second data inputs to receive information appearing at the data inputs mentioned above and to store this information temporarily and also with second outputs to present to the first data inputs mentioned above, whereby a closed path can be formed, for the information, with, also, in the closed path an information-reconstruction device to receive, reconstruct and re-inject all the information circulating in the closed path on the basis of an error-correcting code, in which for n ≥ 4 there is, each time, a processor element with an appropriate section of the memory (28, 30, 32, 34) and a separate reconstruction section (54, 56, 58, 60) of the information reconstruction device in a separate error-isolation area, in which within an error-isolation area is present an encoder (20, 22, 24, 26) based on a data word that is comprised of k symbols, each of b bits, and which is regenerated by the appropriate processor element, to form a code symbol of b bits for the appropriate memory section as part of a code word consisting of n code symbols belonging to a set of code words with a code distance, defined over the symbols thereof, having a value of D (D ≥ 3), in which said second data outputs are each time connected to inputs of all reconstruction sections of the relevant multi-processor computer system so as, each time, to feed, in full, to each reconstruction section word read out from the memory for the purpose of reconstructing the appropriate data word, and in which the relationship between D, k and n is given by the formula: D. k - (D - 1) > n - (D - 1)≥k≥2.
Claim 2
Dependent Claim
318 words
A multi-processor computer system comprising a number n (n) 2) of processor elements operating in parallel (12, 14, 16, 18), each of which have a first data input and a first data output, which computer system further comprises a memory with second data inputs to receive information appearing at the data inputs mentioned above and to store this information temporarily and also with second outputs to present to the first data inputs mentioned above, whereby a closed path can be formed, for the information, with, also, in the closed path an information-reconstruction device to receive, reconstruct and re-inject all the information circulating in the closed path on the basis of an error-correcting code, in which for n ≥ 4 there is, each time, a processor element with an appropriate section of the memory (28, 30, 32, 34) and a separate reconstruction section (54, 56, 58, 60) of the information reconstruction device in a separate error-isolation area, in which within an error-isolation area is present an encoder (20, 22, 24, 26) based on a data word that is comprised of k symbols, each of b bits, and which is regenerated by the appropriate processor element, to form a code symbol of b bits for the appropriate memory section as part of a code word consisting of n code symbols belonging to a set of code words with a code distance, defined over the symbols thereof, having a value of D (D ≥ 3), in which said second data outputs are each time connected to inputs of all reconstruction sections of the relevant multi-processor computer system so as, each time, to feed, in full, to each reconstruction section word read out from the memory for the purpose of reconstructing the appropriate data word, and in which the relationship between D, k and n is given by the formula: D. k - (D - 1) > n - (D - 1)≥k≥2.
Claim 3
Dependent Claim
39 words
Multi-processor computer system according to Claim 1, in which the value of n is given by n = k + D - 1, whereby for D = 4, b\ log (n- 2 ) but otherwise b≥ log 2 (n-1).
Claim 4
Dependent Claim
31 words
Multi-processor computer system according to Claim 1, in which the values of D, b, k and n are given by the relations: D = 3, n = k+2, b≥log 2 (n-1)
Claim 5
Dependent Claim
29 words
Multi-processor computer system according to Claim 3, in which the values of b, k and n are given by the relations: n = 4, k = 2, b 2.
Claim 6
Dependent Claim
30 words
Multi-processor computer system according to Claim 3, in which the encoders are able to accept the elements of the (n-2) data-symbols as elements in the code-symbols mentioned without further coding.
Claim 7
Dependent Claim
34 words
Multi-processor computer system according to anyone of Claims 1 to 5, in which each error-isolation area contains a register for a code-word at the input of the information reconstruction section (46, 48, 50, 52).
Claim 8
Dependent Claim
36 words
Multi-processor computer system according to anyone of Claims 1 to 6, in which at least one of the information-reconstruction sections is provided with a signal output to indicate the detection of a (corrigible or non-corrigible) error.
Claim 9
Dependent Claim
117 words
Multi-processor computer system according to anyone of Claims 1 to 7, in which for the connection of peripheral equipment, in a first error-isolation area, the processor element is provided with at least one outgoing control line (92) and with one outgoing line (90) for a data word for that peripheral equipment, the processor element in all the error-isolation areas is provided with at least one incoming control line and with one incoming line for a data word from that peripheral equipment and in which all the data word and control incoming lines are provided with switches (99, 101, 103, 105) that may be activated in a blocking manner by an output signal from the corresponding processor element.
Claim 10
Dependent Claim
185 words
Multi-processor computer system according to anyone of Claims 1 to 7, in which, for the connection of peripheral equipment, the peripheral equipment is provided with first means (217) to receive the code-symbols from all the error-isolation areas formed by the corresponding encoder therein, and on the basis thereof to reconstruct the corresponding data-word, the processor element in each error-isolation area is provided with at least one outgoing control line for that peripheral equipment and a second encoder (156, 158, 160, 162), the peripheral equipment is provided with second means (217) to form a control word from the coded control signals per error-isolation area on the basis of the same symbol-correcting code as that used for the code-word, the processing element in all the error-isolation areas is provided with at least one incoming control line and with an incoming line for a data-word from that peripheral equipment, and in which all the incoming control and data word lines from the peripheral equipment are provided with switches (292, 294, 296, 298) that can be activated in a blocking manner by an output signal from the processing elements.
Claim 11
Dependent Claim
195 words
Multi-processor computer system according to any one of Claims 1 to 7, in which, for the connection of a peripheral equipment, the peripheral equipment is provided with first means to receive code-symbols from all the error-isolation areas formed by the corresponding encoder and on the basis thereof to reconstruct the corresponding data word and furtherwith third means to form by code- formation as in the error-isolation areas a code-word from a data word produced in each error-isolation area the processor element is provided with at least one outgoing control line for that peripheral equipment and a second encoder, the peripheral equipment is provided with second means to form a control word from the coded control signals per error-isolation area on the basis of the same symbol-correcting code as that used for the code-word, the processor element in each of theerror-isolation areas is provided with at least one incoming control line from that peripheral equipment and in which the information reconstruction section is connected via a switching device that may be activated in a blocking manner by an output signal from the processor element in order to receive a whole code-word generated in the peripheral equipment.
Claim 12
Dependent Claim
271 words
Multi-processor computer system according to anyone of Claims 1 to 7, distributed over first error-isolating areas, in which, for the connection of a peripheral equipment that is distributed over second error-isolation areas, each second error-isolation area is provided with first means (277, 279, 281, 195) to receive' from all first error-isolation areas the code-symbols formed by the corresponding encoder and on the basis thereof to reconstruct the corresponding data word, fourth means (260, 262, 264, 266) are provided to form a code symbol from a data word produced by way of encoding as in a corresponding first error-isolation area; in each first error-isolation area the processor element is provided with at least one outgoing control line for the peripheral equipment and a second encoder, the peripheral equipment is provided in each error-isolation area with second means for the formation of a control word from the coded control signals of each error-isolation area; all first error-isolation areas are provided with fifth means (316, 318, 320, 322) to receive at least one control signal from all second error-isolation areas and to form from them a corresponding combined control signal and to feed this to the corresponding processor element via a switching device (99, 101, 103, 105), which can be actuated in a blocking manner by the said processor element, and in which in all first error-isolation areas the information reconstruction section is connected, via a further switching device (292, 294, 296, 298) which can be actuated in a blocking manner by a second output signal from the corresponding processor element, so as to receive a whole code-word generated in the perpheral equipment mentioned.
Claim 13
Dependent Claim
17 words
Multi-processor computer system according to Claim 10, in which the peripheral equipment contains n second error-isolation areas.
Claim 14
Dependent Claim
149 words
Multi-processor computer system according to anyone of Claims 1 to 6, in which at least one of the information-reconstruction sections is provided with a signal output for signalling an error, including an identification signal for an error-isolation layer in which a symbol error has occurred, in which means are present for holding said identification signals and forming on this basis an erase identification signal, the generator matrix for the parity symbols comprises only symbols that" are determined within a Galois sub-field of the Galois field, within which the data symbols are determined, said means comprise an output for feeding an erase identification signal to inputs of the respective error-isolation areas and the information-reconstruction sections are able, while controlling an erase identification signal, to negate the information signals from an error-isolation area identified by this erase identification signal and, furthermore, to correct a bit error generated outside said error-isolation area.
References Cited (Backward Citations)
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