Memory device

Claim 2

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; characterized in that the address buses (A) or the data buses (B) are formed by paired bus lines (A,a or B,b); and that bridge lines (5 or 4) are formed between one (A or B) and the other (a or b) of the paired bus lines (A,a or B,b).

Claim 3

A memory device comprising: ._ a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; characterized in that the address buses.(A) and the data buses (B) are formed by paired bus lines (A,a and B,b); and that bridge lines (5) are formed between one (A) and the other (a) of the paired address bus lines (A,a); and bridge lines (4) are formed between one (B) and the other (b) of the paired data bus lines (B,b).

Claim 4

A memory device comprising: ._ a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; characterized in that the address buses.(A) and the data buses (B) are formed by paired bus lines (A,a and B,b); and that bridge lines (5) are formed between one (A) and the other (a) of the paired address bus lines (A,a); and bridge lines (4) are formed between one (B) and the other (b) of the paired data bus lines (B,b).

Claim 5

A memory device of claim 1 or 2, wherein test pads (6,7) are formed for the paired bus lines (A,a and/or B,b) for testing whether or not these bus lines form an open circuit and whether or not the adjacent bus lines are short-circuited.

Claim 6

A memory device according to any one of claims 1 to 3, wherein a fuse (8,9) are disposed between the bus line (A,a,B,b) and the test pad (6,7) for electrically interrupting these bus lines.

Claim 7

A memory device according to any one of claims 1 to 4, wherein said memory cell includes: a capacitor electrode (15) insulated from a substrate; a first transistor (11) whose gate electrode is-connected to one (Al) of said paired address buses, a first electrode of said first transistor being connected to one (Bl) of said paired data buses, and a second electrode of said first transistor being connected to said capacitor electrode (15); and a second transistor (12) whose gate electrode is connected to the other (al) of said paired address buses, a first electrode of said second transistor being connected to the other (bl) of said paired data buses, and a second electrode of said second transistor being connected to said capacitor electrode (15).

Claim 8

A memory device of claim 5, wherein said memory cell further includes: a third transistor (13) whose gate electrode is connected to said one (Al) of said paired address buses, a first electrode of said third transistor being connected to said other (bl) of said paired data buses, and a second electrode of said third transistor being connected to said capacitor electrode (15).

Claim 9

A memory device of claim 5, wherein said memory cell further includes: a fourth transistor (14) whose gate electrode is connected to said other (al) of said paired address buses, a first electrode of said fourth transistor being connected to said one (Bl) of said paired data buses, and a second electrode of said third transistor being connected to said capacitor electrode (15).

Claim 10

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that. the address bus driver (35) has output pads; the respective address buses (A) are formed by paired bus lines (A,a) and electrode pads (25) are disposed at least one of both ends of the respective bus lines (A,a); and that the electrode pads (25) connected to the bus line at the non-defective side of the paired bus lines (A,a) of the respective rows are connected to the corresponding output pads of the address bus driver (35), respectively.

Claim 11

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that. the address bus driver (35) has output pads; the respective address buses (A) are formed by paired bus lines (A,a) and electrode pads (25) are disposed at least one of both ends of the respective bus lines (A,a); and that the electrode pads (25) connected to the bus line at the non-defective side of the paired bus lines (A,a) of the respective rows are connected to the corresponding output pads of the address bus driver (35), respectively.

Claim 12

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that the data bus driver (34) has output pads; the respective data buses (B) are formed by paired bus lines (B,b) and electrode pads (26) are disposed at least one of both ends of the respective bus lines (B,b); and that the electrode pads (26) connected to the bus line at the non-defective side of the paired bus lines (B,b) of the respective columns are connected to the corresponding output pads of the data bus driver (34), respectively.

Claim 13

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that the data bus driver (34) has output pads; the respective data buses (B) are formed by paired bus lines (B,b) and electrode pads (26) are disposed at least one of both ends of the respective bus lines (B,b); and that the electrode pads (26) connected to the bus line at the non-defective side of the paired bus lines (B,b) of the respective columns are connected to the corresponding output pads of the data bus driver (34), respectively.

Claim 14

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells .(10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that the address bus driver (35) and the data bus driver (34) have output pads, respectively; the respective address buses (A) are formed by paired bus lines (A,a) and electrode pads (25) are disposed at least one of both ends of the respective bus lines (A,a); and the electrode pads (25) connected to the bus line at the non-defective side of the paired bus lines (A,a) of the respective rows are connected to the corresponding output pads of the address bus driver (35), respectively; and that .the respective data buses (B) are formed by paired bus lines (B,b) and electrode pads (26) are disposed at least one of both ends of the respective bus lines (B,b); and the electrode pads (26) connected to the bus line at the non-defective side of the paired bus lines (B,b) of the respective columns are connected to the corresponding output pads of the data bus driver (34), respectively.

Claim 15

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells .(10) and forming respective rows of said matrix; data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; the address bus driver (35) connected to the address buses (A); and the data bus driver (34) connected to the data buses (B); characterized in that the address bus driver (35) and the data bus driver (34) have output pads, respectively; the respective address buses (A) are formed by paired bus lines (A,a) and electrode pads (25) are disposed at least one of both ends of the respective bus lines (A,a); and the electrode pads (25) connected to the bus line at the non-defective side of the paired bus lines (A,a) of the respective rows are connected to the corresponding output pads of the address bus driver (35), respectively; and that .the respective data buses (B) are formed by paired bus lines (B,b) and electrode pads (26) are disposed at least one of both ends of the respective bus lines (B,b); and the electrode pads (26) connected to the bus line at the non-defective side of the paired bus lines (B,b) of the respective columns are connected to the corresponding output pads of the data bus driver (34), respectively.

Claim 16

A memory device according to any one of claims 8 to 10, wherein said memory cell includes: a capacitor electrode (15) insulated from a substrate; a first transistor (11) whose gate electrode is connected to one (Al) of said paired address buses, a first electrode of said first transistor being connected to one (Bl) of said paired data buses, and a second electrode of said first transistor being connected to said capacitor electrode (15); and a second transistor (12) whose gate electrode is connected to the other (al) of said paired address buses, a first electrode of said second transistor being connected to the other (bl) of said paired data buses, and a second electrode of said second transistor being connected to said capacitor electrode (15).

Claim 17

A memory device of claim ll, wherein said memory cell further includes: a third transistor (13) whose gate electrode is connected to said one (Al) of said paired address buses, a first electrode of said third transistor being connected to said other (bl) of said paired data buses, and a second electrode of said third-transistor being connected to said capacitor electrode (15).

Claim 18

A memory device of claim 11, wherein said memory cell further includes: a fourth transistor (14) whose gate electrode is connected to said other (al) of said paired address buses, a first electrode of said fourth transistor being connected to said one (Bl) of said paired data buses, and a second electrode of said third transistor being connected to said capacitor electrode (15).

Claim 19

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; characterized in that the address buses (A) or the data buses (B) are formed by paired bus lines (A,a or B,b); fuses (36 to 39 or 40 to 43) are disposed at two or more locations of at least one line of the paired bus lines (A,a or B,b); and that means (46,47) for preventing floating of the bus line (Al) is disposed between the bus line (e.g., Al) interposed between, the fuses (e.g., 36 and 37) at two locations and a predetermined potential part (e.g., substrate).

Claim 20

A memory device comprising: a plurality of memory cells (10) arranged in a matrix form; address buses (A) connected to the memory cells (10) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (10) and forming respective columns of said matrix; characterized in that the address buses (A) or the data buses (B) are formed by paired bus lines (A,a or B,b); fuses (36 to 39 or 40 to 43) are disposed at two or more locations of at least one line of the paired bus lines (A,a or B,b); and that means (46,47) for preventing floating of the bus line (Al) is disposed between the bus line (e.g., Al) interposed between, the fuses (e.g., 36 and 37) at two locations and a predetermined potential part (e.g., substrate).

Claim 21

A memory device of claim 14, wherein said floating preventing means includes: " a unidirectional conduction device (46 - 49) which is reversely biased when said address bus (A or a) is not floating and is forwardly biased when said address bus (A or a) is going to float for clamping said address bus at a potential substantially the same as said predetermined potential part (substrate).

Claim 22

A memory device of claim 15, wherein said unidirectional conduction device (46 - 49) comprises a p-n junction diode formed in a semiconductor substrate on which is formed the memory device.

Claim 23

A memory device of claim 14, wherein said floating preventing means includes: a unidirectional conduction device which is reversely biased when said data bus (B or b) is not floating and is forwardly biased when said data bus (B or b) is going to float for clamping said data bus at a potential substantially the same as said predetermined potential part.

Claim 24

A memory device of claim 17, wherein said unidirectional conduction device comprises a p-n junction diode formed in a semiconductor substrate on which is formed the memory device.

Claim 25

A memory device according to any one of claims 14 to 18, wherein said memory cell includes: a capacitor electrode (15) insulated from a substrate; a first transistor (11) whose gate electrode is connected to one (Al) of said paired address buses, a first electrode of said first transistor being connected to one (Bl) of said paired data buses, and a second electrode of said first transistor being connected to said capacitor electrode (15); and a second transistor (12) whose gate electrode is connected to the other (al) of said paired address buses, a first electrode of said second transistor being connected to the other (bl) of said paired data buses, and a second electrode of said second transistor being connected to said capacitor electrode (15).

Claim 26

A memory device of claim 19, wherein said memory cell further includes: a third transistor (13) whose gate electrode is connected to said one (Al) of said paired address buses, a first electrode of said third transistor being connected to said other (bl) of said paired data buses, and a second electrode of said third transistor being connected to said capacitor electrode (15).

Claim 27

A memory device of claim 19, wherein said memory cell further includes: a fourth transistor (14) whose gate electrode is connected to said other (al) of said paired address buses, a first electrode of said fourth transistor being connected to said one (Bl) of said paired data buses, and a second electrode of said third transistor being connected to said capacitor electrode (15).

Claim 28

A memory device comprising: a plurality of memory cells (1) arranged in a matrix form; address buses (A) connected to the memory cells (1) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (1) and forming respective columns of said matrix; characterized by further comprising paired address bus driver means (35 1 ,35 2 ) connected to both ends of said address buses (A), said paired driver means including paired driver blocks (Pl - Pm/2) connected to both ends of said respective address buses (Al - Am), said paired blocks (Pl - Pm/2) outputting same address signals to said address bus interposed between said blocks in synchronism with each other.

Claim 29

A memory device comprising: a plurality of memory cells (1) arranged in a matrix form; address buses (A) connected to the memory cells (1) and forming respective rows of said matrix; and data buses (B) connected to said memory cells (1) and forming respective columns of said matrix; characterized by further comprising paired address bus driver means (35 1 ,35 2 ) connected to both ends of said address buses (A), said paired driver means including paired driver blocks (Pl - Pm/2) connected to both ends of said respective address buses (Al - Am), said paired blocks (Pl - Pm/2) outputting same address signals to said address bus interposed between said blocks in synchronism with each other.

Claim 30

A memory device comprising: a plurality of memory cells (1) arranged in a matrix form; address buses (A) connected to the memory cells (1) and forming respective rows of said matrix; and . data buses (B) connected to said memory cells (1) and forming respective columns of said matrix; characterized by further comprising paired data bus driver means (34 1 ,34 2 ) connected to both ends of said data buses (B), said paired driver means including paired driver blocks (Pl - Pm/2) connected to both ends of said respective data buses (Bl - Bn), said paired blocks (Pl - Pm/2) outputting same data signals to said data bus interposed between said blocks in synchronism with each other.

Claim 31

A memory device comprising: a plurality of memory cells (1) arranged in a matrix form; address buses (A) connected to the memory cells (1) and forming respective rows of said matrix; and . data buses (B) connected to said memory cells (1) and forming respective columns of said matrix; characterized by further comprising paired data bus driver means (34 1 ,34 2 ) connected to both ends of said data buses (B), said paired driver means including paired driver blocks (Pl - Pm/2) connected to both ends of said respective data buses (Bl - Bn), said paired blocks (Pl - Pm/2) outputting same data signals to said data bus interposed between said blocks in synchronism with each other.