Semiconductor memory device

Claim 2

A semiconductor devic having a semiconductor substrate (41); at least one insulating gate FET transistor (Ql) comprising a source region and a drain region formed in the semiconductor substrate (41), and a gate electrode (46) formed on a gate insulation film overlying a channel formed between said source and drain regions; and a first current path including said channel of said insulation gate FET transistor (Ql) and a conductive path connected to said channel and overlying said semiconductor substrate (41), characterized in that a second current path including at least one polycrystalline silicon layer (R2) for a load overlying said gate electrode (46) is provided, and that the first current path is so provided as to be isolated from the second current path.

Claim 3

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FET transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said one first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate (41); and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2) which is adapted to act as a driver transistor for an inverter, and that the first current path is so provided as to be isolated from the second current path.

Claim 4

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FET transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said one first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate (41); and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2) which is adapted to act as a driver transistor for an inverter, and that the first current path is so provided as to be isolated from the second current path.

Claim 5

A semiconductor device according to any one of claims 1 and 2, characterized in that at least said first gate electrode (46) is a low specific resistance polycrystalline silicon layer in which is injected an impurity at a high concentration, and the entirety of said high specific resistance polycrystalline silicon layer has a substantially uniform impurity concentration.

Claim 6

A semiconductor device according to any one of claims 1 and 2, characterized in that at least said first gate electrode (46) is a low specific resistance polycrystalline silicon layer in which is injected an impurity at a high concentration, and said high specific resistance polysrystalline silicon layer comprises a low impurity concentration polycrystalline silicon layer formed continuously with a high impurity concentration polycrystalline silicon layer.

Claim 7

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FE T transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said one first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate; and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one first polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said first polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2), that another polycrystalline silicon layer (Rl) overlying said second gate electrode (44) is connected as a load of said first insulation gate FET transistor (Ql), and that the first current path is so provided as to be isolated from the second current path.

Claim 8

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FE T transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said one first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate; and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one first polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said first polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2), that another polycrystalline silicon layer (Rl) overlying said second gate electrode (44) is connected as a load of said first insulation gate FET transistor (Ql), and that the first current path is so provided as to be isolated from the second current path.

Claim 9

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FET transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said on first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate; and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one first polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said first polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2), that another polycrystalline silicon layer (Rl) overlying said second gate electrode (44) is connected as a load of said first insulation gate FET transistor (Ql), that the first current path is so provided as to be isolated from the second current path, that said first gate electrode (46) is connected to a juncture between said first polycrystalline silicon layer (R2) included in said second current path and the drain region of said second insulation gate FET transistor (Q2), and that said second gate electrode (44) is connected to a juncture between said second polycrystalline silicon layer (Rl) included in said first current path and the drain region of said first insulation gate FET transistor (Ql), thereby constituting a filp-flop.

Claim 10

A semiconductor device having a semiconductor substrate (41); at least one first insulation gate FET transistor (Ql) comprising a first source region and a first drain region formed in the semiconductor substrate (41), and a first gate electrode (46) formed on a first gate insulation film overlying a first channel formed between said first source and drain regions; a first current path including said first channel of said on first insulation gate FET transistor (Ql) and a conductive path connected to the first channel and overlying said semiconductor substrate; and at least one other second insulation gate FET transistor (Q2) having a second source region, a second drain region, and a second gate electrode (44) formed on a second gate insulation film overlying a second channel formed between said second source and drain regions; characterized in that a second current path including said second channel and at least one first polycrystalline silicon layer (R2) overlying said first gate electrode (46) is provided, that said first polycrystalline silicon layer (R2) is connected as a load of said second insulation gate FET transistor (Q2), that another polycrystalline silicon layer (Rl) overlying said second gate electrode (44) is connected as a load of said first insulation gate FET transistor (Ql), that the first current path is so provided as to be isolated from the second current path, that said first gate electrode (46) is connected to a juncture between said first polycrystalline silicon layer (R2) included in said second current path and the drain region of said second insulation gate FET transistor (Q2), and that said second gate electrode (44) is connected to a juncture between said second polycrystalline silicon layer (Rl) included in said first current path and the drain region of said first insulation gate FET transistor (Ql), thereby constituting a filp-flop.

Claim 11

A semiconductor device as claimed in any one of claims 1 through 6 characterized in that part of at least one (100) of said first and second polycrystalline silicon layers is substantially directly contacted with the surface of any (107) of said first and second source or drain regions.

Claim 12

A semiconductor device comprising, on a semiconductor substrate (41) of one conductivity type, a first region (42) of opposite conductivity type having first, second, third and fourth extensions (42a, 42b, 42c, 42d) integrally extending in the directions of a row and column through one contact (C) on a major surface of said semiconductor device, said extensions (42a - 42d) defining sections (I - IV) of said major surface of said semiconductor substrate lying between said first through fourth extensions (42a - 42d) as first through fourth memory cell forming regions having said contact (C) as a center; each of said first through fourth memory cell forming regions (I - IV) having a polycrystalline silicon power source line (V ss ) including a second region (45) of oppsite conductivity type to form a first driver transistor (Ql) between said one extension (42d) and said second region (45); a third region (43) of opposite conductivity type to form a second driver transistor (Q2) between said other extension (42a) and said third region (43); a fourth region(47) of the opposite conductivity type to form a first switching transistor (Q3) between said second region (45) and said fourth region (47); fifth and sixth regions (48, 49) of the opposite conductivity type to form a second switching transistor (Q4) arranged next to said first switching transistor (Q3) in the direction of the row; a first polycrystalline silicon gate electrode (46) of L-shape formed between said first and second regions (42, 45) through a gate insulation layer, one end of which extends in direction of the column to be connected with said fifth region (48) and the other end of which extends in the direction of the row to be connected with said third region (43); a second polycrystalline silicon gate electrode (44) of L-shape formed between said first and third regions (42, 43) in the direction of the column through a gate insulation layer, one end of which extends in the direction of the row to be connected with said second region (45); a polycrystalline silicon word line (Wl) formed in the direction of the row as a common gate electrode of said first and second switching transistors (Q3, Q4) through a gate insulation layer; a first high specific resistance polycrystalline silicon layer (R2) formed above said first polycrystalline silicon gate electrode (46) through an insulation layer, one end of which forms a substantially direct contact being directly in contact with a junction of said fifth region (48) and said first polycrystalline silicon gate electrode (46) and which is used as a load for said second driver transistor (Q2), and a second high specific resistance polycrystalline silicon layer (Rl) formed above said second polycrystalline gate electrode (44) with a insulation layer therebetween, one end of which forms a substantially direct contact being directly in contact with a junction of said second region (45) and said second polycrystalline silicon gate electrode (44) and which is used as a load for said first driver transistor (Ql); a metal ground line (V ss ) formed in the direction of the column through an insulation layer so as to pass above said contact (C) for connection with said first region (42); and first and second metal data lines (Dl, Dl) arranged next to the direction of the column corresponding to said first and second switching transistors (Q3, Q4).

Claim 13

A semiconductor device comprising, on a semiconductor substrate (41) of one conductivity type, a first region (42) of opposite conductivity type having first, second, third and fourth extensions (42a, 42b, 42c, 42d) integrally extending in the directions of a row and column through one contact (C) on a major surface of said semiconductor device, said extensions (42a - 42d) defining sections (I - IV) of said major surface of said semiconductor substrate lying between said first through fourth extensions (42a - 42d) as first through fourth memory cell forming regions having said contact (C) as a center; each of said first through fourth memory cell forming regions (I - IV) having a polycrystalline silicon power source line (V ss ) including a second region (45) of oppsite conductivity type to form a first driver transistor (Ql) between said one extension (42d) and said second region (45); a third region (43) of opposite conductivity type to form a second driver transistor (Q2) between said other extension (42a) and said third region (43); a fourth region(47) of the opposite conductivity type to form a first switching transistor (Q3) between said second region (45) and said fourth region (47); fifth and sixth regions (48, 49) of the opposite conductivity type to form a second switching transistor (Q4) arranged next to said first switching transistor (Q3) in the direction of the row; a first polycrystalline silicon gate electrode (46) of L-shape formed between said first and second regions (42, 45) through a gate insulation layer, one end of which extends in direction of the column to be connected with said fifth region (48) and the other end of which extends in the direction of the row to be connected with said third region (43); a second polycrystalline silicon gate electrode (44) of L-shape formed between said first and third regions (42, 43) in the direction of the column through a gate insulation layer, one end of which extends in the direction of the row to be connected with said second region (45); a polycrystalline silicon word line (Wl) formed in the direction of the row as a common gate electrode of said first and second switching transistors (Q3, Q4) through a gate insulation layer; a first high specific resistance polycrystalline silicon layer (R2) formed above said first polycrystalline silicon gate electrode (46) through an insulation layer, one end of which forms a substantially direct contact being directly in contact with a junction of said fifth region (48) and said first polycrystalline silicon gate electrode (46) and which is used as a load for said second driver transistor (Q2), and a second high specific resistance polycrystalline silicon layer (Rl) formed above said second polycrystalline gate electrode (44) with a insulation layer therebetween, one end of which forms a substantially direct contact being directly in contact with a junction of said second region (45) and said second polycrystalline silicon gate electrode (44) and which is used as a load for said first driver transistor (Ql); a metal ground line (V ss ) formed in the direction of the column through an insulation layer so as to pass above said contact (C) for connection with said first region (42); and first and second metal data lines (Dl, Dl) arranged next to the direction of the column corresponding to said first and second switching transistors (Q3, Q4).

Claim 14

A semiconductor memory system having a first memory cell matrix (122), a second memory cell matrix (123), a first decoder (121) for selecting one line of a predetermined number of row lines and column lines of either of said first and second memory cell matrices (122, 123), a second decoder (120) for selecting one line crossing said selected line among said column and row lines of said first and second memory cell matrices (122, 123), and an I/O bus line (124) for outputting data read out from a selected memory cell matrix selected from said first and second memory cell matrices (122, 123) by outputs of said first and second decoders (121, 120); characterized in that each memory cell constituting said first and second memory cell matrices (122, 123) has first and second driver transistors (Ql, Q2) formed in a semiconductor substrate, first and second polycrystalline silicon layer loads (R2, Rl) formed above said first and second driver transistors (Ql, Q2) with an insulation layer therebetween, means for connecting in series said second polycrystalline silicon layer load (Rl) formed above said second driver transistor (Q2) as a load in a first current path including said first driver transistor (Ql), and means for connecting in series said first polycrystalline silicon layer load (R2) formed above said first driver transistor (Ql) as a load in a second current path including said second driver transistor (Q2).

Claim 15

A semiconductor memory system having a first memory cell matrix (122), a second memory cell matrix (123), a first decoder (121) for selecting one line of a predetermined number of row lines and column lines of either of said first and second memory cell matrices (122, 123), a second decoder (120) for selecting one line crossing said selected line among said column and row lines of said first and second memory cell matrices (122, 123), and an I/O bus line (124) for outputting data read out from a selected memory cell matrix selected from said first and second memory cell matrices (122, 123) by outputs of said first and second decoders (121, 120); characterized in that each memory cell constituting said first and second memory cell matrices (122, 123) has first and second driver transistors (Ql, Q2) formed in a semiconductor substrate, first and second polycrystalline silicon layer loads (R2, Rl) formed above said first and second driver transistors (Ql, Q2) with an insulation layer therebetween, means for connecting in series said second polycrystalline silicon layer load (Rl) formed above said second driver transistor (Q2) as a load in a first current path including said first driver transistor (Ql), and means for connecting in series said first polycrystalline silicon layer load (R2) formed above said first driver transistor (Ql) as a load in a second current path including said second driver transistor (Q2).

Claim 16

A semiconductor memory system as claimed in claim 9 characterized in that parts of said first and second polycrystalline silicon layer loads (R2, Rl) are respectively formed as substantially direct contacts being directly in contact with the surface of an active region constituting said first and second driver transistors (Ql, Q2).

Claim 17

A semiconductor memory system characterized by comprising a first memory cell matrix (122), a second memory cell matrix (123), a first decoder (121) for selecting one line of a predetermined number of row lines and column lines of either of said first and second memory cell matrices (122, 123), a second decoder (120) for selecting one line crossing said selected line among said column and row lines of said first and second memory cell matrices (122, 123), and an I/O bus line (124) for delivering data read out from a selected memory cell matrix selected from said first and second memory cell matrices (122, 123) by outputs of said first and second decoders (121, 120).

Claim 18

A semiconductor memory system characterized by comprising a first memory cell matrix (122), a second memory cell matrix (123), a first decoder (121) for selecting one line of a predetermined number of row lines and column lines of either of said first and second memory cell matrices (122, 123), a second decoder (120) for selecting one line crossing said selected line among said column and row lines of said first and second memory cell matrices (122, 123), and an I/O bus line (124) for delivering data read out from a selected memory cell matrix selected from said first and second memory cell matrices (122, 123) by outputs of said first and second decoders (121, 120).