Abstract Detector circuit transistors TL1, TL2 detect read currents Is1, ls2 from memory cells (one cell shown includes transistors TC1, TC2, resistors RL and diode R1) for delivery to inputs of a sense amplifier SA. The bases of transistors TL1, TL2 are crossconnected to provide a hysteresis characteristic when a current 11 is supplied by hysteresis control circuit HC. Current 11 is supplied when the potential on line Vwc is less than a predetermined potential Vrs. The potential on line Vwc is the logical sum of the potentials on driving word lines Vws, Vwn. In an address undecided region during address changeover the potentials on word lines Vws, Vwn are all less than Vrs, current 11 is supplied, and the hysteresis characteristic holds the inputs to sense amplifier SA in their previous state so that equal inputs are not applied. When the new address is decided a word line potential exceeds Vrs, the hysteresis characteristic is removed, and inputs to sense amp SA can change rapidly.
A semiconductor memory having a memory cell array including a plurality of memory cells, and having a plurality of word lines and a plurality of bit lines for selecting a desired one of the memory cells, and a detector circuit for detecting a read current of a selected memory cell of the memory cell array, characterised in that the detector circuit includes a pair of transistors having their bases cross-connected to provide a hysteresis characteristic which is obtained by applying a current to the transistors, and a hysteresis characteristic control circuit which monitors the potentials of the pluralityZtord lines and delivers a current for providing the hysteresis characteristic only when the potentials of all the word lines of the plurality have become lower than a predetermined potential.
Claim 2
Dependent Claim
127 words
A semiconductor memory having a memory cell array including a plurality of memory cells, and having a plurality of word lines and a plurality of bit lines for selecting a desired one of the memory cells, and a detector circuit for detecting a read current of a selected memory cell of the memory cell array, characterised in that the detector circuit includes a pair of transistors having their bases cross-connected to provide a hysteresis characteristic which is obtained by applying a current to the transistors, and a hysteresis characteristic control circuit which monitors the potentials of the pluralityZtord lines and delivers a current for providing the hysteresis characteristic only when the potentials of all the word lines of the plurality have become lower than a predetermined potential.
Claim 3
Dependent Claim
45 words
A memory as claimed in claim 1, wherein the hysteresis control circuit monitors the potentials of the word lines by comparing the potential state of a line on which the logical sum of the potentials of the word lines is provided with the predetermined potential.
Claim 4
Dependent Claim
57 words
A memoryas claimed in claim 2, wherein the said logical sum is provided through the connection of the outputs of a plurality of word line potential selection/non-selection detection circuits in common to the said line on which the logicalsum is provided, inputs of respective such word line potential selection/non-selection detection circuits being connected to respective word lines.
Claim 5
Dependent Claim
48 words
A memory as claimed in any preceding claim, wherein the respective collectors of the respective transistors of the pair are connected to respective read current lines via respective further transistors, for cutting off parasitic capacitances, which are supplied with bias current to hold them ON at all times.
Claim 6
Dependent Claim
33 words
A memory as claimed in claim 4, wherein the said current for providing the hysteresis characteristic is supplied to the transistors of the pair via an additional transistor, for cutting off parasitic capacitances.
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