Patent EP0023847A2 successfully refreshed from Google Patents.
EP0023847A2
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EP
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Semiconductor circuit for a dynamic random access memory
Assignee: NEC Corp
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Filing: 1980-08-07
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Granted: —
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Expires: 2000-08-07
Abstract
Abstract The circuit can maintain a high level of a sampled signal on an output node O 11 without decay in level. When the input level sampled by Q 13 rises, complementary output nodes N 11 and N 12 of a delay circuit B1 initially remain at ''1'' and ''0'' and a capacitor C 11 charges through Q 11 . When N 12 switches to '1' after the delay, a node N 13 goes more positive than V DD and turns a transistor switch 0 12 hard on to connect V DD to O 11 . In other embodiments the delay circuit drives the transistor switch through a bootstrap circuit.
Inventors
- 👤 Shoji Ishimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 11:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01742; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/4096; G11C7/00; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
74 words
A semiconductor circuit comprising an input node, an output node, a transfer circuit responsive to a control circuit to couple the input node to the output node, and a power supply terminal, characterised by switching means (Q12; Q 29 ; Q 47 ) connected between the power supply terminal (V DD ) and the output node, and a control circuit responsive to a level of the output node for selectively closing the switching means.
Claim 2
Dependent Claim
74 words
A semiconductor circuit comprising an input node, an output node, a transfer circuit responsive to a control circuit to couple the input node to the output node, and a power supply terminal, characterised by switching means (Q12; Q 29 ; Q 47 ) connected between the power supply terminal (V DD ) and the output node, and a control circuit responsive to a level of the output node for selectively closing the switching means.
Claim 3
Dependent Claim
50 words
A circuit according to claim 1, characterised in that switching means includes a first insulated gate field effect transistor (Q 12 ; Q 29 ; Q 47 ) having its drain coupled to the power supply terminal (V DD ), its source coupled to the output node, and a gate.
Claim 4
Dependent Claim
103 words
A circuit according to claim 2, characterised in that the control means includes a delay circuit (Bl) having an input coupled to the output node, and inverted and non-inverted outputs (N 11 and N12), a second insulated gate field effect transistor (Q 11 ) having its gate coupled to the inverted output (N 11 ), its drain coupled to the output node (011) and its source coupled to the gate of the first transistor (Q 12 ), and a capacitor coupled between the gate of the first transistor (Q 12 ) and the non-inverted output (N 12 ) of the delay circuit (Bl).
Claim 5
Dependent Claim
47 words
A circuit according to claim 2, characterised in that the control circuit comprises a bootstrap circuit (Q 27 , Q 28' C 21 ) having an input coupled to the output node (0 21 ) and an output coupled to the gate of the first transistor (Q29).
Claim 6
Dependent Claim
187 words
A circuit according to claim 4, characterised in that the bootstrap circuit comprises a second insulated gate field effect transistor (Q 27 ) having its drain coupled to the power supply terminal (V DD ), and its gate coupled to the gate of the first transistor (Q 24 ), a third transistor (Q 28 ) having its drain coupled to the source of the second transistor (Q 27 ), and its source coupled to the ground potential, a delay circuit (Q 22 -Q 25 ) having an input coupled to the output node (0 21 ) and an output (N 22 ) coupled to the gate of the third transistor (Q 28 ), a fourth insulated gate field effect transistor (Q 30 ) having its drain coupled to the output node (0 21 ), and its source coupled to the gate of the second transistor (Q27), a capacitor (C 21 ) connected between the gate and the source of the second transistor, and a circuit connection coupled between the gate of the fourth transistor (Q 30 ) and the output (N 22 ) of the delay circuit.
Claim 7
Dependent Claim
34 words
A circuit according to any of claims 1 to 5, further characterised by a flip-flop circuit (Q 31 -Q 34 ) which establishes the logical level on the input node '(N 31 ) '
Claim 8
Dependent Claim
29 words
A circuit according to any of claims 1 to 6, further characterised by a reset circuit (Q31) for operatively resetting a level of the output node (O 21 ).
Claim 9
Dependent Claim
43 words
A circuit according to any of claims 1 to 7, characterised in that the control circuit is so responsive to the level of the output node to close the switch when the level of the output node is near the power supply voltage.
References Cited (Backward Citations)
No citation records indexed.
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