Data processing apparatus with a reconfigurable key based main storage protect mechanism

Claim 2

Data processing apparatus having a plurality of data storage units (BSU's) together forming the main storage of the apparatus, a key based main storage protect mechanism and a plurality of storage controllers (SGO, SG1), each providing for access to all the data storage units of the main storage characterized in that the main storage protect mechanism comprises a key-in-storage array (KIS) in each storage controller together with means (16, 17, 18, 19) to interrogate the same, a cross-interrogation bus (10) interconnecting each interrogation means whereby, in response to a storage access attempt by any one storage controller, all the key-in-storage arrays are interrogated in parallel, no one key-in-storage array having a key storage capacity sufficient for the keys necessary to protect the whole of the main storage.

Claim 3

Apparatus as claimed in claim 1 characterized in that each key-in-storage array is divided into a plurality of groups (SP) of key storage elements each group being of a capacity corresponding to a predetermined range of absolute addresses in the main storage, the interrogation means including, for each group, a range identifier register (18), a comparator (19) and a key storage element accessing mechanism (16, 17), the comparator being responsive to the contents of the range identifier register and to a first predetermined set of bits of a presented address, whether locally generated or supplied via the cross-interrogate bus, to permit an output from the group if a match is determined, the key storage element accessing mechanism being responsive to a second predetermined set of bits of the presented address to access one key storage element of the group.

Claim 4

Apparatus as claimed in claim 2 characterized in that each key is responsible for the protection of a block of consecutive absolute main storage addresses, the first and second sets of address bits being sufficient, taken together, to distinguish one block of physical addresses from another, the grouping being such that the blocks protected by the keys stored in the key storage elements of that group have the first set of address bits in common.

Claim 5

Apparatus as claimed in claim 3 characterized in that the first set of address bits are high order address bits, and in that the range identifier register is (re) loadable.

Claim 6

Apparatus as claimed in claim 1 characterized in that the main storage is (re) organizable on a block interleaved basis, a storage request register is provided to receive the absolute address of each storage request and in that each key-in-storage array comprises a plurality of key storage element SP groups each group having at least one array chip (c), at least one SP address register (14) for receiving bits of each absolute address in the storage request register, the absolute address having: a BSM bit position which switches at main storage boundaries equal to the size of a BSM, and a block-related bit position which switches at main storage boundaries equal to an integral multiple of the size of a block, means connecting the bit positions of the absolute address in the storage request register (13) to corresponding bit positions in the SP address register in the absolute address sequence of bits except that the block-related bit position is connected out-of-sequence to adjacently follow the BSM bit position in the SP address register, the SP address register being divided into at least a high-order field and a low-order field, the high-order field having both the BSM bit position and the block-related bit position, the interrogation means including decoder means (16, 17) in each SP group having an input connected to the low-order field of the SP address register, the decoder output being connected to the chips in the same SP group for locating an SP entry in the group, a range identifier register (18) in each SP group containing a value defining a particular absolute address range related to the size of a BSM, a comparator (19) in each SP group having one input connected to the high-order field in the SP address register, another input to the comparator connected to the range identifier register in the same SP group, gating means (G) with each SP group connected to the output of the comparator and to the output of the chip(s) in the same SP group for outputting the SP entry located by the decoder means, and array output registering means (21), connected to the gating means of all SP groups in the array.

Claim 7

Apparatus as claimed in claim 5 characterized in that each SP group comprises a plurality of array chips (Cl, C2, C3, C4), the gating means comprises a chip output gate for each chip, an intermediate field being defined in the SP address register between the high-order field and the low-order field, the decoder means comprises a chip decoder (16) connected to the intermediate field for selecting a particular chip output gate, and a location decoder (17) connected to the low-order field for locating an entry in the chip connected to the particular chip output gate, and the gating means (GO) outputting the selected chip output gate to the array output registering means only in response to an output from the comparator.

Claim 8

Apparatus as claimed in claim 5 or claim 6 characterized in that a system console is provided, equipped to load a different BSM range value into range identifier register whereby the SP groups in the SP array are arranged to operate associatively in relation to the requests.

Claim 9

Apparatus as claimed in any preceding claim characterized in that there is provided array output registering.means (21) with each array for receiving a key entry should such be found in that array, the cross-interrogation bus and having lines gating means for cross coupling the output of each array output registering means to the input of the other array output registering means, each storage control unit also comprising: a priority circuit (42) receiving local and remote requests and outputting priority selection signals indicating which request is selected as a current request to the local array, a timing chain (43) actuated by the priority circuit whenever it gives priority to each current request, an end operation trigger (44) reset by each current request outputted from the priority circuit, the end operation trigger set by an output of the timing chain, indicating means (41) for each array for indicating whether an entry is found in the respective array for the current request, output means (46) connected to a found output of the indicating means and to a remote priority output of the priority circuit for outgating the local array output registering means to the bus, and ingate means (47) connected to a not-found output of the indicating means and to a local priority output from the priority circuit for ingating the bus to the local array output registering means.