Abstract A decoder circuit for a semiconductor memory device having a short build-up time for the potential on the decoder lines whilst using only a limited number of constant current sources in the decoder comprises a sequence of address signal input terminals (A0, A1, ...) a number of address buffers (21,22, ...) a number of pairs of decoder lines d0, d0, d1, d1, ...) connected to the address buffers with each pair of the decoder lines being connected between its address buffer and a constant current source (S2), a major part of the current from each constant current source (S2) passing through only one decoder line of each pair at any instant, a sequence of word lines (W0, W1, W2, ...) and a number of word drivers (41, 42) each having a matrix of diodes (D1,D2, ...) of a multi-emitter transistor (Qm). This arrangement halves the number of current sources used with the decoder lines and eliminates those used in the word drivers whilst not increasing the build-up time of potentials applied to the decoder lines.
A decoder circuit for a semiconductor memory device, comprising a sequence of address signal input terminals, a number of address buffers, each of which includes a gate circuit for producing an address signal and an inverted address signal, a constant current source, and transistors connected in an emitter follower configuration for each output of the gate circuit, a number of pairs of decoder lines connected to the address buffers with one of each pair being connected to the output of its address buffer producing the address signal and the other of each pair being connected to the output of its address buffer producing the inverted address signal, each pair of the decoder lines being connected between its address buffer and a constant current source, a major part of the current from each constant current source passing through only one decoder line of each pair at any instant, a sequence of word lines, and a number of word drivers each having a matrix of diodes or a multi-emitter transistor, a resistor circuit connected to a power source , and a transistor connected to one of the word lines, one end of each of the diodes or each emitter of the multi-emitter transistor being connected to one of the decoder lines and the other end of each diode or the collector of the multi-emitter transistor being connected to a junction of the resistor circuit and the base of said transistor connected to one of the word lines.
Claim 2
Dependent Claim
245 words
A decoder circuit for a semiconductor memory device, comprising a sequence of address signal input terminals, a number of address buffers, each of which includes a gate circuit for producing an address signal and an inverted address signal, a constant current source, and transistors connected in an emitter follower configuration for each output of the gate circuit, a number of pairs of decoder lines connected to the address buffers with one of each pair being connected to the output of its address buffer producing the address signal and the other of each pair being connected to the output of its address buffer producing the inverted address signal, each pair of the decoder lines being connected between its address buffer and a constant current source, a major part of the current from each constant current source passing through only one decoder line of each pair at any instant, a sequence of word lines, and a number of word drivers each having a matrix of diodes or a multi-emitter transistor, a resistor circuit connected to a power source , and a transistor connected to one of the word lines, one end of each of the diodes or each emitter of the multi-emitter transistor being connected to one of the decoder lines and the other end of each diode or the collector of the multi-emitter transistor being connected to a junction of the resistor circuit and the base of said transistor connected to one of the word lines.
Claim 3
Dependent Claim
16 words
A decoder circuit according to claim 1, wherein switching transistors are inserted in each decoder line.
Claim 4
Dependent Claim
24 words
A decoder circuit according to claim 1 or 2, further comprising additional constant current sources connected to each of the pairs of decoder lines.
Claim 5
Dependent Claim
36 words
A decoder circuit cccording to claim 2 or claim 3, when dependent upon claim 2, further comprising circuits including level shifting diodes for supplying signals to the bases of the switching transistors in the decoder lines.
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