Encoder for length or angle measuring devices with high accuracy

Claim 2

An encoder for measuring devices having first scale means (10) arranged in a given regular fashion and forming a first scale for measuring a length or an angle, second scale means (14) arranged in opposition to the first scale and forming a second scale corresponding to the first scale, and processor means (20) for interpolating one pitch of the first or the second scale on the basis of a relative position of the first scale to the second scale, characterized in that the first scale of the first scale means (10) is formed by a code plate (10) including a plurality of binary grating patterns (12, GP), and the second scale of the second scale means (14) is comprised of a sensor array (14) including individual sensor elements (16), and that the number of the binary grating patterns (12, GP) in opposition to a given range of the second scale is different from the number of the sensor elements (16) within the same range, and, when one of the first and second scales is a main scale, the other is a vernier scale; the processor means (20) performs the interpolation depending on the reading data (RI) produced from the sensor array (14) in accordance with a relative position of the binary grating patterns (12, GP) to the sensor elements (16).

Claim 3

An encoder according to claim 1, wherein said code plate (10) includes a plurality of blocks (11 i ) arranged in serial fashion, each block including a plurality of grating patterns (GP), a reference pattern (REF) for indicating a reference position of each block and having a pattern arrangement different from that of the binary grating pattern (GP), a block address pattern (AP) for indicating an absolute position of the block and having a pattern arrangement different from that of the binary grating pattern (GP); said senior array (14) has such a size as to substantially cover at least one block; said processor means (20) measures a length or an angle with the unit of one pitch of the first or second scale by using reading data (RI) on the basis of the reference pattern (REF) produced from the sensor array (14) and the block pattern (AP).

Claim 4

An encoder according to claim 2, wherein said binary grating pattern (GP) includes two kinds of patterns of which the transmittances of light are different with a given ratio therebetween; the block address pattern (AP) includes two kinds of patterns of which the transmittances of light are different with a given ratio therebetween; said sensor elements (16) are comprised of optoelectric converting elements; said first scale means (10) includes optical system (18, 19 and 22 to 30) for illuminating the sensor array (14) through the binary grating pattern (GP) and the block address pattern (AP); wherein said optoelectric converting elements (16) convert a light distribution projected on said sensor array (14) through said binary grating pattern (GP) and the block address pattern (AP) into said reading data (RI).

Claim 5

An encoder according to claim 1 or 2, wherein said binary grating pattern (GP) is comprised of a group of slits (12) in which two kinds of patterns of which the transmittances of light are different with a given ratio therebetween are periodically arranged; said sensor elements (16) are comprised of optoelectric converting elements; said first scale means (10) includes an optical system (18, 19, 22 to 30) for illuminating the sensor array (14) through said slit group (12); wherein said optoelectric converting elements (16) convert a light distribution projected on said sensor array (14) through said slit group (12) into said reading data (RI).

Claim 6

An encoder according to claim 2, wherein said binary grating pattern (GP) are comprised of a first magnet pattern including two kinds of magnetic poles of which magnetic flux states are different with a given ratio therebetween: the block address pattern (AP) is comprised of a second magnet pattern including two kinds of magnet poles of which magnetic flux states are different with a given ratio therebetween; said sensor elements (16) are comprised of electromagnetic converting elements; wherein said electromagnetic converting elements convert the magnetic fluxes developed from said first and second magnet patterns onto said sensor elements (16) into said reading data (RI).

Claim 7

An encoder according to claim 1, 2 or 5 wherein said binary grating pattern (GP) is comprised of a group of magnets in which two kinds of magnetic poles of which the magnetic flux states are different with a given ratio therebetween are periodically arranged; said sensor elements (16) are comprised of electromagnetic converting elements; wherein said electromagnetic converting elements convert a magnetic flux distribution developed by said magnetic group (12) onto said sensor elements (16) into said reading data (RI).

Claim 8

An encoder according to claim 2, wherein said binary grating pattern (GP) are comprised of a first electret pattern including two kinds of electrodes of which dielectric flux states are different with a given ratio therebetween; the block address pattern (AP) is comprised of a second electret pattern including two kinds of electrodes of which dielectric flux states are different with a given ratio therebetween; said sensor elements (16) are comprised of electrostatic converting elements; wherein said electrostatic converting elements convert the dielectric flux developed from said first and second electret patterns onto said sensor elements (16) into said reading data (RI).

Claim 9

An encoder according to claim 1, 2 or 7 wherein said binary grating pattern (GP) is comprised of a group of clectrets in which two kinds of electrodes of which the dielectric flux states arc different with a given ratio therebetween are periodically arranged; said sensor elements (16) are comprised of electrostatic converting elements; wherein said electrostatic convcrting elements convert a dielectric flux distribution developed by said electret group (12) onto said sensor elements (16) into said reading data (RI).

Claim 10

An encoder according to claim 1, 2, 3, 5 or 7, wherein said processor means (20) includes first means (200) for successively producing said reading data (RI) from said sensor elements (16) by using clock pulses (el); second means (214 to 220, 230, 234) for detecting a point (X) where a phase of an oscillation representing a level change of said reading data (RI) successively produced in synchronism with the clock pulse (el); third means (222) for counting the clock pulses (el) from a given start point until said phase inverting point (X) is detected or from said phase inverting point (X) until a given end point is detected; wherein said interpolation is performed on the basis of the result of the counting in said third means (222).

Claim 11

An encoder according to claim 4, wherein said processor means (20) includes first means (200) for successively producing said reading data (RI) from said sensor elements (16) by using clock pulses (el); second means (214 to 220, 230 234) for detecting a point (X) where a phase of an oscillation representing a level change of said reading data (RI) successively produced in synchronism with the clock pulse (el); third means (222) for counting the clock pulses (el) from a given start point until said phase inverting point (X) is detected or from said phase inverting point (X) until a given end point is detected; wherein said interpolation is performed on the basis of the result of the counting in said third means (222).

Claim 12

An encoder according to claim 6, wherein said processor means (20) includes first means (200) for successively producing said reading data (RI) from said sensor elements (16) by using clock pulses (el); second means (214 to 220, 230, 234) for detecting a point (X) where a phase of an oscillation representing a level change of said reading data (RI) successively produced in synchronism with the clock pulse (el); third means (222) for counting the clock pulses (el) from a given start point until said phase inverting point (X) is detected or from said phase inverting point (X) until a given end point is detected; wherein said interpolation is performed on the basis of the result of the counting in said third means (222).

Claim 13

An encoder according to claim 8, wherein said processor means (20) includes first means (200) for successively producing said reading data (RI) from said sensor elements (16) by using clock pulses (el); second means (214 to 220, 230, 234) for detecting a point (X) where a phase of an oscillation representing a level change of said reading data (RI) successively produced in synchronism with the clock pulse (el); third means (222) for counting the clock pulses (el) from a given start point until said phase inverting point (X) is detected or from said phase inverting point (X) until a given end point is detected; wherein said interpolation is performed on the basis of the result of the counting in said third means (222).

Claim 14

An encoder according to claim 9, wherein said second means (214 to 220, 230 234) includes fourth means (214) for classifying said reading data (RI) successively read out in synchronism with the clock pulse (el) into odd number data (e3 i ) produced from said odd numbered sensor elements (16 i ) and even number data (e3 i+1 ) produced from said even numbered sensor elements (16 i+1 ); fifth means (216) for detecting an envelope (OL) of the levels of the odd number data classified by said fourth means (214) to produce an odd number envelope signal (e9); sixth means (218) for detecting an envelope (EL) of the levels of the even number data classified by said fourth means (214) to produce an even number envelope signal (e10); and seventh means (220) which compares the odd number envelope signal (e9) produced from said fifth means (216) with the even number envelope signal (e10) produced from said sixth moans (218), and applies a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222) when both said signals (e9) and (e10) are substantially the same in level.

Claim 15

An encoder according to claim 10, wherein said second means (214 to 220, 230, 234) includes fourth means (214) for.classifying said reading data (RI) successively read out in synchronism with the clock pulse (el) into odd number data (e3 i ) produced from said odd numbered sensor elements (16 i ) and even number data (e3 i+1 ) produced from said even numbered sensor elements (16 i+1 ); fifth means (216) for detecting an envelope (O L ) of the levels of the odd number data classified by said fourth means (214) to produce an odd number envelope signal (e9); sixth means (218) for detecting an envelope (EL) of the levels of the even number data classified by said fourth means (214) to produce an even number envelope signal (elO); and seventh means (220) which compares the odd number envelope signal (e9) produced from said fifth means (216) with the even number envelope signal (elO) produced from said sixth means (218), and applies a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222) when both said signals (e9) and (e10) are substantially the same in level.

Claim 16

An encoder according to claim 11, wherein said second means (214 to 220, 230, 234) includes fourth means (214) for classifying said reading data (RI) successively read out in synchronism with the clock pulse (el) into odd number data (e3 i ) produced from said odd numbered sensor elements (16 i ) and even number data (c3 i+1 ) Produced from said even numbered sensor elements (16 i+1 ); fifth means (216) for detecting an envelope (OH) of the levels of the odd number data classified by said fourth means (214) to produce an odd number envelope signal (e9); sixth means (218) for detecting an envelope (EL) of the levels of the even number data classified by said fourth means (214) to produce an even number envelope signal (elO); and seventh means (220) which compares the odd number envelope signal (e9) produced from said fifth means (216) with the even number envelope signal (e10) produced from said sixth means (218), and applies a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222) when both said signals (e9) and (elO) are substantially the same in level.

Claim 17

An encoder according to claim 12, wherein said second means (214 to 220, 230, 234) includes fourth means (214) for classifying said reading data (RI) successively read out in synchronism with the clock pulse (el) into odd number data (e3 i ) produced from said odd numbered sensor elements (16 i ) and even number data (e3 i+1 ) produced from said even numbered sensor elements (16 i+1 ); fifth means (216) for detecting an envelope (OL) of the levels of the odd number data classified by said fourth means (214) to produce an odd number envelope signal (e9); sixth means (218) for detecting an envelope (EL) of the levels of the even number data classified by said fourth means (214) to produce an even number envelope signal (e10); and seventh means (220) which compares the odd number envelope signal (e9) produced from said fifth means (216) with the even number envelope signal (elO) produced from said sixth means (218), and applies a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222) when both said signals (e9) and (elO) are substantially the same in level.

Claim 18

An encoder according to claim 9, wherein said second means (214 to 220, 230, 234) includes an eighth means (234) which detects a reading data representing approximate medium level between the maximum and the minimum levels of said reading data (RI) successively read out in synchronism with the clock pulse (el) to apply a phase inverting signal (ell) representing said phase inverting point (X) to said third moans (222).

Claim 19

An encoder according to claim 10, wherein said second means (214 to 220, 230, 234) includes an eighth means (234) which detects a reading data representing approximate medium level between the maximum and the minimum levels of said reading data (RI) successively read out in synchronism with the clock pulse (el) to apply a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222).

Claim 20

An encoder according to claim 11, wherein said second means (214 to 220, 230, 234) includes an eighth means (234) which detects a reading data representing approximate medium level between the maximum and the minimum levels of said reading data (RI) successively read out in synchronism with the clock pulse (el) to apply a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222).

Claim 21

An encoder according to claim 12, wherein said second means (214 to 220, 230, 234) includes an eighth means (234) which detects a reading data representing approximate medium level between the maximum and the minimum levels of said reading data (RI) successively read out in synchronism with the clock pulse (el) to apply a phase inverting signal (ell) representing said phase inverting point (X) to said third means (222).

Claim 22

An encoder according to claim 9, wherein said second means (214 to 220, 230, 234) includes ninth means (230) which compares the phase of a comparing signal (e ) with such a phase as to correspond to said reading data (RI) successively outputted in synchronism with the clock pulse (el), with the phase of a reference signal (e r ) with such a phase as to correspond to the clock pulse (el), and which produces a phase inverting signal (ell) reprosenting said phase inverting point (X) when a phase relation between the compering signal (e x ) and the reference signal (e r ) is inverted.

Claim 23

An encoder according to claim 10, wherein said second means (214 to 220, 230, 234) includes ninth means (230) which compares the phase of a comparing signal (e x ) with such a phase as to correspond to said reading'data (RI) successively outputted in synchronism with the clock pulse (el), with the phase of a reference signal (e r ) with such a phase as to correspond to the clock pulse (el), and which produces a phase inverting signal (ell) representing said phase inverting point (X) when a phase relation between the comparing signal (e ) x and the reference signal (e ) is inverted.

Claim 24

An encoder according to cliam 11, wherein said second means (214 to 220, 230, 234) includes ninth means (230) which compares the phase of a comparing signal (e x ) with such a phase as to correspond to said reading data (RI) successively outputted in synchronism with the clock pulse (el), with the phase of a reference signal (e ) with such a phase as to correspond to the clock pulse (el), and which produces a phase inverting signal (ell) representing said phase inverting point (X) when a phase relation between the comparing signal (e x ) x and the reference signal (e ) is inverted.

Claim 25

An encoder according to cliam 11, wherein said second means (214 to 220, 230, 234) includes ninth means (230) which compares the phase of a comparing signal (e x ) with such a phase as to correspond to said reading data (RI) successively outputted in synchronism with the clock pulse (el), with the phase of a reference signal (e ) with such a phase as to correspond to the clock pulse (el), and which produces a phase inverting signal (ell) representing said phase inverting point (X) when a phase relation between the comparing signal (e x ) x and the reference signal (e ) is inverted.

Claim 26

An encoder according to claim 12, wherein said second means (214 to 220, 230 234) includes ninth means (230) which compares the phase of a comparing signal (e ) with such a phase as to correspond to said reading data (RI) successively outputted in synchronism with the clock pulse (el), with the phase of a reference signal (e r ) with such a phase as to correspond to the clock pulse (el), and which produces a phase inverting signal (ell) representing said phase inverting point (X) when a phase relation between the comparing signal (e x ) and the reference signal (e r ) is inverted.

Claim 27

An encoder according to claim 2, 3, 5 or 7, wherein said processor means (20) includes first means (200) for successviely producing said reading data (RI) from said sensor elements (16) by using a clock pulse (el); ninth means (250) for detecting a start bit (SB) determined on the basis of the reference pattern (REF) from the reading data (RI) successively produced in synchronism with the clock pulse (el); tenth means (258) for detecting a given index bit (IB) in said sensor elements (16); eleventh means (252, 256, 259) for counting the clock pulse (el) produced during a time period from an instant that the start bit (SB) is detected until the index bit (IB) is detected; twelfth means (254, 260, 264) for taking out the reading data (RI) corresponding to the binary grating pattern (GP) during a time period from a first bit (K) to a second bit (K+k) since the start bit (SB) is detected; thirteenth means (254, 262, 270) for taking out the reading data (RI) corresponding to the block address pattern (AP) during a time period from a third bit (M) to a fourth bit (M+m) since the start bit (SB) is detected; and fourteenth means (262, 266, 268, 272, 274) which determines an absolute position of a block on the basis of the reading data (RI) produced from said thirteenth means (254, 262, 270), determines a coarse reading value with a unit of one pitch of the second scale on the basis of the count result obtained by said eleventh means (252, 256, 259), and determines an interpolation value of one pitch of the second scale on the basis of the reading data (RI) produced from said twelfth means (254, 260, 264), and in which a relative displacement of the code plate (10) to said sensor array (14) is determined by the block absolute position, the coarse reading value, and the interpolation value.

Claim 28

An encoder for measuring devices having first scale means (10) arranged in a given regular fashion and forming a first scale for measuring a length or an angle, second scale means (14) arranged in opposition to the first scale and forming a second scale corresponding to the first scale, and processor moans (20) for interpolating one pitch of the first or the second scale on the basis of a relative position of the first scale to the second scale, characterized in that the first scalc of the first scale means (10) is formed by a code plate (10) including a plurality of binary grating patterns (12, GP), and the second scale of the second scale moans (14) is comprised of a sensor array (14) including individual sensor elements (16), and that the number of the binary grating patterns (12, GP) in opposition to a given range of the second scale is different from the number of the sensor elements (16) within the same range, and, when one of the first and second scales is a main scale, the other is a vernier scale; the processor means (20) performs the interpolation depending on the reading data (RI) produced from the sensor array (14) in accordance with a relative position of the binary grating patterns (12, GP) to the sensor elements (16), and the range for the interpolation is larger than the one pitch of the first or the second scale.

Claim 29

An encoder for measuring devices having first scale means (10) arranged in a given regular fashion and forming a first scale for measuring a length or an angle, second scale means (14) arranged in opposition to the first scale and forming a second scale corresponding to the first scale, and processor moans (20) for interpolating one pitch of the first or the second scale on the basis of a relative position of the first scale to the second scale, characterized in that the first scalc of the first scale means (10) is formed by a code plate (10) including a plurality of binary grating patterns (12, GP), and the second scale of the second scale moans (14) is comprised of a sensor array (14) including individual sensor elements (16), and that the number of the binary grating patterns (12, GP) in opposition to a given range of the second scale is different from the number of the sensor elements (16) within the same range, and, when one of the first and second scales is a main scale, the other is a vernier scale; the processor means (20) performs the interpolation depending on the reading data (RI) produced from the sensor array (14) in accordance with a relative position of the binary grating patterns (12, GP) to the sensor elements (16), and the range for the interpolation is larger than the one pitch of the first or the second scale.

Claim 30

An encoder according to claim 26, wherein the range for the interpolation is substantially equal to double pitch of the first or the second scale.