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EP0010344A1
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Digital signal detector
Assignee: Motorola Solutions Inc
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Filing: 1979-08-13
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Granted: —
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Expires: 1999-08-13
Abstract
Abstract A digital signal detector is disclosed that detects a serial bit stream transmitted at a predetermined bit frequency. Bit transistors are totalized in a counter (115) over a predetermined time interval. Bit transistions occurring during a good window interval from gate (111) increment the totalized count by one. Bit transistions occurring during a bad window interval from gate (112) decrement the totalized count by one. Bit transistions occurring during a marginal window interval from gate (110), situated between the good and bad window intervals, do not affect the totalized count. If the counter (115) reaches a predetermined count during the time interval, a detect signal is provided by flip flop (117) indicating that the digital signal has been detected. The counter (115) can be further loaded with a threshold count for tailoring the digital signal detector for operation at a particular signal-to-noise ratio. Periodic signals that have frequencies that are submultiples of the bit frequency are detected by correlating the digital signal between two predetermined stages of a shift register (<sub>101</sub>). The digital signal detector may provide a detector output signal when both the digital signal is detected atflip flop (117) and periodic signals having submultiple frequencies are not present at flip flop 106).
Inventors
- 👤 Terence Edward Sumner
- 👤 Charles Alphonsus Backof Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 13:52
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/446; H04Q1/448; H04Q1/4485; G; G01; G01R; G01R23/00; G01R23/02; G01R23/15; G01R23/155; H04L; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
231 words
A detector for a digital signal transmitted in a serial bit stream at a predetermined bit frequency by a clock signal, characte ized in that: first counting means (107, 108) responsive to the clock signal for providing a reset pulse signal at the end of each N bit interval, where N is an integer; transition detection means (113, 114) responsive to the digital signal and the clock signal for providing a transition pu e signal for each change in logical state between s ssive bits of the digital signal; window ge erating means (109-112) responsive to the clock signal for repetitively generating during each bit interval a plurality of window signals, each window signal having a corresr nding predetermined value that is predeterminedly related to the probability of bit transitions occurring in the interval of the respective window signal; second counting means (115) responsive to the reset pulse signals and transition pulse signals for providing for each N bit interval, a totalized count formed by totalizing for each transition pulse signal, the predetermined value corresponding to the window signal during which the respective transition pulse signal occurs; and means for comparing (115, 116, 117) each totalized count from the second counting means to a first threshold count and providing an indication signal indicating that the digital signal is present when the respective totalized count is greater than the first threshold count.
Claim 2
Dependent Claim
231 words
A detector for a digital signal transmitted in a serial bit stream at a predetermined bit frequency by a clock signal, characte ized in that: first counting means (107, 108) responsive to the clock signal for providing a reset pulse signal at the end of each N bit interval, where N is an integer; transition detection means (113, 114) responsive to the digital signal and the clock signal for providing a transition pu e signal for each change in logical state between s ssive bits of the digital signal; window ge erating means (109-112) responsive to the clock signal for repetitively generating during each bit interval a plurality of window signals, each window signal having a corresr nding predetermined value that is predeterminedly related to the probability of bit transitions occurring in the interval of the respective window signal; second counting means (115) responsive to the reset pulse signals and transition pulse signals for providing for each N bit interval, a totalized count formed by totalizing for each transition pulse signal, the predetermined value corresponding to the window signal during which the respective transition pulse signal occurs; and means for comparing (115, 116, 117) each totalized count from the second counting means to a first threshold count and providing an indication signal indicating that the digital signal is present when the respective totalized count is greater than the first threshold count.
Claim 3
Dependent Claim
88 words
The digital signal detector according to claim 1, characterized in that the window generating means (109-112) generates at least first, second and third nonoverlapping window signals, the first window signal substantially centered about the transition of the clock signal that is in synchronism with the bit transitions of the digital signal, the second window signal substantially centered about the transition of the clock signal that is in quadrature with the bit transitions of the digital signal, the third window signal disposed between the first and second window signals.
Claim 4
Dependent Claim
43 words
The digital signal detector according to claim 2, characterized in that the intervals of the first and second window signals are substantially identical, and the interval of the third window signal is smaller than the intervals of the first and second window signals.
Claim 5
Dependent Claim
48 words
The digital signal detector according to claim 2, characterized in that the interval of the first window signal is greater than the intervals of the second and third window signals, and the interval of the second window signal is greater than the interval of the third window signal.
Claim 6
Dependent Claim
116 words
5: The digital signal detector according to claim 2, characterized in that the interval of the first window signal includes the portion of each bit interval for which the probability of bit transitions is greater than a first threshold probability; the interval of the third window signal includes the portion of each bit interval for which the probability of bit transitions is less than the first threshold probability and greater than a second threshold probability, where the first threshold probability is greater than the second threshold probability; and the interval of the second window signal includes the portion of each bit interval for which the probability of bit transitions is less than the second threshold probability.
Claim 7
Dependent Claim
48 words
The digital signal detector according to claim 1, characterized in that the comparing means (115, 116, 117) includes means for providing a second threshold count less than the first threshold count for comparisons subsequent to a comparison where the totalized count is greater than the first threshold count.
Claim 8
Dependent Claim
41 words
The digital signal detector according to claim 3, characterized in that the first window signal has a corresponding value of +1, the second window has a corresponding value of -1 and the third window signal has a corresponding value of zero.
Claim 9
Dependent Claim
265 words
The digital signal detector according to claim 1, further characterized by means for detecting a plurality of periodic signals in the bit stream at submultiple fre q uen- cies of the bit frequency, the period of the periodic signals being 2N times the period of the bit frequency, where N is an integer, said periodic signal detecting means including: first register means (101) having a predetermined number of stages, the first register means responsive to the clock signal for serially receiving the digital signal and providing at least first and second delayed bits, B 1 and B I+M , respectively, the first delayed bit B 1 provided by stage I, and the second delayed bit B I+M provided by stage I+tl, stage I+M delayed by M bits relative to stage I, where I is an integer and M is the lowest common multiple of the factors 2N for each of the periodic signals; gating means (102) for combining the first and second delayed bits to provide an output signal when the first and second delayed bits have the same logical state; and third counting means (103, 104) responsive to the clock signal, reset pulse signal and output signals of the gating means for providing totalized counts of the gating- means output signals occurring between successive reset pulse signals; and said comparing means (103, 104, 105, 106) further comparing each totalized count from the third counting means to a third reference count and providing an indication signal indicating that a periodic signal is present when the- respective totalized count is greater than the third threshold count.
Claim 10
Dependent Claim
36 words
The digital signal detector according to claim 8, characterized in that the second delayed bit of the first register means (101) is delayed relative to the first delayed bit by a predetermined multiple of M stages.
Claim 11
Dependent Claim
258 words
The digital signal detector according to claim 1, further characterized by-means for detecting a plurality of periodic signals in the bit stream at submultiple frequencies of the bit frequency, the period of the periodic signals being 2N times the period of the bit frequency, where N is an integer, said periodic signal detecting means including: first register means (101) having a predetermined number of stages, the first register means responsive to the clock signal for serially receiving the digital signal and providing at least first and second delayed bits, B I and B I+M , respectively, the first delayed bit B I provided by stage I, and the second delayed bit B I+M provided by stage I+M, stage I+M delayed by M bits relative to stage I, where I is an integer and M is the lowest common multiple of the factors 2N for each of the periodic signals; gating means (102) for combining the first and second delayed bits to provide an output signal when the first and second delayed bits have the opposite logical state; and third counting means (103, 104) responsive to the clock signal, reset pulse signal and output signals of the gating means for providing totalized counts of the gating- means output signals occurring between successive reset pulse signals; and said comparing means (103-106) further comparing each totalized count from the third counting means to a third reference count and providing an indication- signal indicating that a periodic signal is present when the respective totalized count is less than the third threshold count.
Claim 12
Dependent Claim
36 words
The digital signal detector according to claim 10, characterized in that the second delayed bit of the first register means (101) is delayed relative to the first delayed bit by a predetermined multiple of M stages.
Claim 13
Dependent Claim
30 words
The digital signal detector according to claim 8 or 10, further characterized by a semiconductive substrate, said digital signal detector comprised of electrical circuit elements integrated into the semiconductive substrate.
Claim 14
Dependent Claim
76 words
The digital signal detector according to claim 1, characterized in that said window generating means (109-112) generates at least first and second predeterminedly overlapping window signals,the first window signal substantially centered about the transition of the clock signal that is in synchronism with the bit transitions of the digitial signal, and the second window signal substantially centerd about the transition of the clock signal that is in quadrature with the bit transitions of the digital signal.
Claim 15
Dependent Claim
129 words
The digital signal detector according to claim 13, characterized in that said second counting means (115) includes first and second transition counters; the first transition counter incremented by the predetermined value corresponding to the first window signal for each transition pulse signal occurring during the interval of the first window signal; and the second transition counter incremented by the predetermined value corresponding to the second window signal for each transition pulse signal occurring during the interval of the second window signal; and said comparing means including means for comparing for each N bit interval the totalized counts of the first and second transition counters and providing the indication signal when the totalized count of the first transition counter is greater than the totalized count of the second transition counter.
Claim 16
Dependent Claim
43 words
The digital signal detector according to claim 14, characterized in that said comparing means (115-117) provides the indication signal when the totalized count of the first transition counter is greater than the totalized count of the second transition counter by a predetermined amount.
References Cited (Backward Citations)
US3566280A
Cited
US3721905A
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