Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
83 words
A multiplex information handling system comprising a plurality of transmitters and a plurality of receivers all interconnected by a signal bus pieces of control equipment associated with the transmitters and receivers responsive to signals received by an associated receiver along the signal bus characterised in that timing means are provided operative to produce a clock pulse which is as short or shorter than any other pulse transmitted to assist the pulse to be recognised as such by the or each receiver receiving it.
Claim 2
Dependent Claim
83 words
A multiplex information handling system comprising a plurality of transmitters and a plurality of receivers all interconnected by a signal bus pieces of control equipment associated with the transmitters and receivers responsive to signals received by an associated receiver along the signal bus characterised in that timing means are provided operative to produce a clock pulse which is as short or shorter than any other pulse transmitted to assist the pulse to be recognised as such by the or each receiver receiving it.
Claim 3
Dependent Claim
49 words
A multiplex information handling system as claimed in Claim 1, characterised in that the timing means are operative to produce opposite logic levels to the clock pulse itself immediately preceding and succeeding it, each opposite logic level being for a duration equal to the duration of the clock pulse.
Claim 4
Dependent Claim
40 words
'3. A multiplex information handling system as claimed in Claim 1 or 2, characterised in that two or more data bits are transmitted after each clock pulse, the bits progressively increasing in-duration the further they are from the clock pulse.
Claim 5
Dependent Claim
60 words
A multiplex information handling system as claimed in Claim 1, 2 or 3, characterised in that each transmitter is operative to produce a synchronising pulse at the beginning of each transmission which is longer than any other combination of directly adjacent data pulses in the transmission so that it can be recognised as such by a receiver receiving the transmission.
Claim 6
Dependent Claim
46 words
A multiplex information handling system as claimed in Claim 4, characterised in that each transmitter is operative to produce a synchronisation pulse having a length which is dependant upon the transmitter type from which it issues whereby a receiver receiving a transmission can identify that type.
Claim 7
Dependent Claim
37 words
A multiplex information handling system as claimed in any preceding claim, characterised in that the timing means are adapted to be reset in the event of a selected transition in the logic state on the signal bus.
Claim 8
Dependent Claim
30 words
A multiplex information handling system as claimed in any preceding claim, characterised in that means are provided for applying a signal to the signal bus to inhibit transmission or reception.
Claim 9
Dependent Claim
44 words
A multiplex information handling system as claimed in any preceding claim, characterised in that a power bus is provided interconnecting the receivers and transmitters, each transmitter incorporates means for protecting the transmission of analogue data against variation in the voltage on the power bus
Claim 10
Dependent Claim
22 words
A multiplex information handling system as claimed in Claim 8, characterised in that the means for protecting incorporates a constant current source.
Claim 11
Dependent Claim
40 words
A multiplex information handling system as claimed in any preceding claim, characterised in that each transmitter or receiver is fed from the power bus via a resistor and a capacitor and zener diode are connected in parallel with the circuit.
Claim 12
Dependent Claim
33 words
A multiplex information handling system as claimed in Claim 10, characterised in that the signal bus is clamped to the positive and negative terminals of the transmitter . or receiver by respective diodes.
Claim 13
Dependent Claim
47 words
A multiplex information handling system as claimed in Claim 11, characterised in that the base emitter junction of a transistor is connected in the signal bus, the emitter of the transistor being connected to the junction of the two diodes and the collector to the power bus.