Patent CA1272291A successfully refreshed from Google Patents.
CA1272291A
Expired / Lapsed
CA
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Expert system or production rule processor
Assignee: Individual
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Filing: 1989-04-03
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Granted: 1990-07-31
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Expires: 2009-04-03
Abstract
Abstract ABSTRACT Many attempts have been made to design a suitable computer architecturefor processing production systems in parallel and/or in real time. This invention is a processor that can execute production systems such as expert systems or rule based algorithm in real time by processing the rules in parallel. it is based on an arrangement of special gates that permit the firing of several rules concurently. It also does the match of the premisses of rules with the input or conclusions of fired rules in parallel. Once programmed with a production system, the arrangement of gates becomes an analog processor for that particular production system. Several variation or improvement are possible for application to particular fields such as control systems, expert systems, logic programming. The differences permit simpler designs when backward chaining, negation or arithmetic capabilities are not needed.
Inventors
- 👤 Edward Charles Valentine
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-11-03 23:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4496
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
214 words
In a logic performing arrangement including an array having a plurality of condition lines intersected by a plurality of rule lines with logical gates located at at least some intersections of condition and rule lines such that said gates i) in the "don't care" mode let signals flow along all lines passing through them; ii) in the "premisse-true" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "true signal" along its condition line; iii) in the "premisse-false" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "false signal" along their condition line, iv) in the "conclusion-true" mode send a "true signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; v) in the "conclusion-false" mode send a "false signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; some or all of the condition lines can receive external input signals, said signals being either "true signals" or "false signal"; the signals along some or all condition lines can be send along external output lines.
Claim 2
Dependent Claim
214 words
In a logic performing arrangement including an array having a plurality of condition lines intersected by a plurality of rule lines with logical gates located at at least some intersections of condition and rule lines such that said gates i) in the "don't care" mode let signals flow along all lines passing through them; ii) in the "premisse-true" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "true signal" along its condition line; iii) in the "premisse-false" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "false signal" along their condition line, iv) in the "conclusion-true" mode send a "true signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; v) in the "conclusion-false" mode send a "false signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; some or all of the condition lines can receive external input signals, said signals being either "true signals" or "false signal"; the signals along some or all condition lines can be send along external output lines.
Claim 3
Dependent Claim
149 words
In a logic performing arrangement including an array having a plurality of condition lines intersected by a plurality of rule lines with logical gates located at at least some intersections of condition and rule lines such that said gates i) in the "don't care" mode let signals flow along all lines passing through them; ii) in the "premisse-true" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "true signal" along its condition line; iii) in the "conclusion-true" mode send a "true signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; some or all of the condition lines can receive an external input signal, said signal being "true signals"; the signals along some or all condition lines can be send along external output lines.
Claim 4
Dependent Claim
149 words
In a logic performing arrangement including an array having a plurality of condition lines intersected by a plurality of rule lines with logical gates located at at least some intersections of condition and rule lines such that said gates i) in the "don't care" mode let signals flow along all lines passing through them; ii) in the "premisse-true" mode let the signal flow along their rule line to all gates on the same rule line, only when it receives a "true signal" along its condition line; iii) in the "conclusion-true" mode send a "true signal" along their condition line to all gates on the same condition line when they receive a signal on their rule line; some or all of the condition lines can receive an external input signal, said signal being "true signals"; the signals along some or all condition lines can be send along external output lines.
Claim 5
Dependent Claim
28 words
The logic performing array of claim 1 wherein the condition line is replaced by a pair o, condition lines one for true signals the other for false signals.
Claim 6
Dependent Claim
79 words
The logic performing array of claim 3 where each said pair of condition lines is equipped with a contradiction detector that sends an output signal whenever there are signals in both the true and false lines of said condition line or whenever they are in the conclusion and they are receiving a signal along their rule line and another on their condition line, said signal on their condition line being different from the one they are programmed to send.
Claim 7
Dependent Claim
70 words
The logic performing arrangement of claim 4 where said contradiction detectors can inhibit the signal in the condition line unless a predetermined number of gates on that line have initiated a signal or whenever the difference between the number of gates initiating a true signals and the is the number of gates initiating a false signal is less than a predetermined positive value and greater than a predetermined negative value.
Claim 8
Dependent Claim
36 words
The logic performing arrangement of claims 1, 2 or 5 where the logical gates do not have the "don't care" mode, the unused gates simply being removed from the intersection of their rule and condition lines.
Claim 9
Dependent Claim
31 words
The logic performing arrangement of claims 1, 2, or 5 where any of the said logical gates can be placed on more than one intersection of rule lines and condition lines.
Claim 10
Dependent Claim
38 words
The logic performing arrangement of claim 5, wherein conditions can send an interrogating signal to all rules of which they are a conclusion, those rules in turn sending an interrogating signal to all conditions which are their premisses.
Claim 11
Dependent Claim
22 words
The logic performing array of claim 8 where some conditions can be specified as a goal automatically triggering the said interrogating process.
Claim 12
Dependent Claim
45 words
The logic performing array of claims 1, 2, or 5 where the conditions are separated in two groups one having only the premisse mode, the other having only the conclusion mode, the signals of the conclusion mode being fed back to the corresponding premisse condition.
Claim 13
Dependent Claim
78 words
The logic performing arrangement of claims 1, 2 or 5 as part of a dynamically programmed system wherein secondary memory is used to store sets of rules and values of signals along condition lines; the said sets of rules can be programmed into the array one at a time, with input signals being fetched from secondary memory; output signals along condition lines is then stored in secondary memory and another set of rules is programmed into the array.
Claim 14
Dependent Claim
91 words
The logic performing arrangement of claims 1, 2,or 5 where some or all said condition lines are connected to a co-processor, said co-processors having arithmetic and/or logic capabilities or being Von-Neumann style processors having partial or full instruction sets; said co-processors having or not the capacity of sharing data busses and secondary memory, can react to signal in the condition line they are on, according to their own program and can also initiate a signal on said condition line according to said program; said co-processors having or not individual memory store.
Claim 15
Dependent Claim
90 words
The logic performing arrangement of claims 1, 2 or 5 where some or all said gates are connected to a co-processor, said co processors having arithmetic and/or logic capabilities or being Von-Neumann style processors having partial or full instruction sets; said co-processors having or not the capacity o-f sharing data busses and secondary memory, can react to signal in the condition and rule lines they are on according to their own program and can also reprogram the gate according to said program; said co-processors having or not individual memory store.
References Cited (Backward Citations)
No citation records indexed.
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