Computer vector multi-processing control

Claim 2

A multiprocessor memory system comprising: a central memory having a plurality of access paths, said central memory comprised of a plurality of independently addressable banks organized into a plurality of sections, said access paths being distributed among said sections; a plurality of processing machines each connected to said central memory access paths through a plurality of ports, said ports for receiving central memory reference requests from said processing machines and for generating and controlling memory references to said central memory through said access paths; and memory reference conflict resolution means connected to each of said ports for coordinating and prioritizing conflicting memory reference attempts to said central memory, said conflict resolution means including a plurality of conflict resolution circuits equal in number to said memory sections and each controlling the procession of memory references to one of said sections, each of said resolution circuits receiving references associated with said section, and including means for checking the readiness of a bank for referencing and holding a reference until the bank is ready if need be and including means for monitoring all references for identifying conflicts between references being attempted as between different ports an holding all but one of conflicting references to the same bank.

Claim 3

A multiprocessor memory system comprising: a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths; a plurality of processing machines; each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections; and conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving referenced from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits receiving references to its corresponding section from any one of said ports and selectively conveying the references to the access paths for the section, said circuits each including. means for checking the readiness of a bank to be referenced and holding a reference to a busy bank until the bank is ready; means for detecting simultaneously pending references to the same bank and holding all but one reference; and means communicating with said ports and the other of said conflict resolution circuits to cause a port to suspend generation of further references when a reference from that port is being held and to cause the other of said conflict resolution circuits which have received a reference from a port issued subsequent to a held reference generated by that port to hold that reference until all priorly generated references from that port have proceeded so that references to the memory are kept in the order generated.

Claim 4

A multiprocessor memory system comprising: a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths; a plurality of processing machines; each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections; and conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving referenced from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits receiving references to its corresponding section from any one of said ports and selectively conveying the references to the access paths for the section, said circuits each including. means for checking the readiness of a bank to be referenced and holding a reference to a busy bank until the bank is ready; means for detecting simultaneously pending references to the same bank and holding all but one reference; and means communicating with said ports and the other of said conflict resolution circuits to cause a port to suspend generation of further references when a reference from that port is being held and to cause the other of said conflict resolution circuits which have received a reference from a port issued subsequent to a held reference generated by that port to hold that reference until all priorly generated references from that port have proceeded so that references to the memory are kept in the order generated.

Claim 7

A multiprocessor memory system comprising: a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths: a plurality of processing machines equal in number to said plurality of access paths; each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections; and conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving references from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits connected to each of said ports for said processing machines so that any port in any one of said processing machines may access any section and bank in said central memory, said circuit organized so that all references from ports in a given processing machine are directed through a single one of said access paths so that each processing machine has a corresponding access path, each of said circuits including: (a) bank detection means for determining which of said memory banks within the memory section asso-ciated with said circuit has been requested; (b) bank busy conflict means for determining whether the requested memory bank is ready to be referenced or is busy; (c) means for determining whether said circuit has received simultaneous reference requests to the memory section associated with said circuit from multiple ports of the same processing machine: (d) means for determining whether said circuit has received simultaneous reference requests to any one bank within the memory section associated with said circuit from ports of different processing machines; (e) resolution means for resolving bank busy conflicts, conflicts between simultaneous referen-ces from ports of the same processing machine, and conflicts between simultaneous references from ports of different processing machines so that only one memory reference to any one memory bank is allowed at one time, only one memory reference to the memory section associated with said circuit from any one processing machine is allowed at one time, and all memory references from any one port proceed in the order in which the references were generated.

Claim 8

A multiprocessor memory system comprising: a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths: a plurality of processing machines equal in number to said plurality of access paths; each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections; and conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving references from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits connected to each of said ports for said processing machines so that any port in any one of said processing machines may access any section and bank in said central memory, said circuit organized so that all references from ports in a given processing machine are directed through a single one of said access paths so that each processing machine has a corresponding access path, each of said circuits including: (a) bank detection means for determining which of said memory banks within the memory section asso-ciated with said circuit has been requested; (b) bank busy conflict means for determining whether the requested memory bank is ready to be referenced or is busy; (c) means for determining whether said circuit has received simultaneous reference requests to the memory section associated with said circuit from multiple ports of the same processing machine: (d) means for determining whether said circuit has received simultaneous reference requests to any one bank within the memory section associated with said circuit from ports of different processing machines; (e) resolution means for resolving bank busy conflicts, conflicts between simultaneous referen-ces from ports of the same processing machine, and conflicts between simultaneous references from ports of different processing machines so that only one memory reference to any one memory bank is allowed at one time, only one memory reference to the memory section associated with said circuit from any one processing machine is allowed at one time, and all memory references from any one port proceed in the order in which the references were generated.

Claim 9

The multiprocessor memory system of claim 4 wherein said resolution means of each of said conflict resolution circuit comprises: (a) means for assigning priority to ports of the same processing machine simultaneously refer-encing the memory section associated with said circuit according to a predetermined priority scheme; (b) means for assigning priority between said processing machines on an alternating basis; (c) means for handling conflicts between ports of the same processing machine so that the highest priority port with no bank busy conflict and no simultaneous reference from a different processing machine conflict is allowed to proceed; (d) means for handling simultaneous references from different processing machines conflicts so that the port of the highest priority processing machine with no bank busy conflict and no conflict with another port of the same processing machine is allowed to proceed.

Claim 10

The multiprocessor memory system of claim 5 wherein said resolution means further comprises: means for holding all memory references that have bank busy conflicts, conflicts with simultaneous references from the same processing machine or conflicts with simultaneous references from a different processing machine.

Claim 11

The multiprocessor memory system of claim 6 wherein said resolution means further comprises: means for signalling all ports that have a reference being held at said circuit so that said ports do not generate another memory reference request.

Claim 12

The multiprocessor memory system of claim 6 wherein said resolution means further comprises: means for signalling all other conflict resolution circuits that have received a memory reference request from a port issued subsequent to a held reference generated by that port so that memory reference requests from that port are kept in the order generated.