Patent CA1229928A successfully refreshed from Google Patents.
← Back to Patent Explorer
CA1229928A Expired / Lapsed CA ⏱️ 0.0 years remaining

Adaptive, non-iterating processor for iterative functions

Assignee: MARINCO COMPUTER PRODUCTS Inc
•
Filing: 1985-05-24
•
Granted: 1987-12-01
•
Expires: 2005-05-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract ADAPTIVE, NON-ITERATING PROCESSOR FOR ITERATIVE FUNCTIONS ABSTRACT OF THE DISCLOSURE A method and apparatus in a data processing system for accomplishing the equivalent of an iterative process rapidly and non-iteratively to dramatically enhance computational speed, the system being self-adap-tive, so that the value of a pre-programmed variable N in a program instruction is determined during a computa-tional run and is stuffed into the processing system and written over the N-field of a microprocessor, whereby computation can be carried out directly and non-iteratively in a single cycle, as though the N variable had been a known constant at the time of programming.

Inventors

  • 👤 Robert A. Parker
  • 👤 Edward L. Davis

Bibliographic Details

Application Number —
Jurisdiction CA
Data Source google_patents
Last Synchronized 2026-11-05 17:18
CPC Classifications
—

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 66 words
An adaptive data processing system for performing iterative functions, non-iteratively, said system comprising: a processor having an N-field input; first means for monitoring program instruc-tions to said processor; second means for providing a generated value of N during running of the system; and third means, responsive to said first means, for jamming the N-value provided by said second means into the N-field input of said processor.
Claim 2
Dependent Claim 66 words
An adaptive data processing system for performing iterative functions, non-iteratively, said system comprising: a processor having an N-field input; first means for monitoring program instruc-tions to said processor; second means for providing a generated value of N during running of the system; and third means, responsive to said first means, for jamming the N-value provided by said second means into the N-field input of said processor.
Claim 3
Dependent Claim 15 words
A system as set forth in Claim 1, wherein said processor includes a barrel shifter.
Claim 4
Dependent Claim 109 words
An adaptive data processing system for performing iterative functions, non-iteratively, said system comprising: an arithmetic logic unit having an N-field input, said arithmetic logic unit including means for executing an N-iterative function directly in a rapid non-iterative manner; first means for monitoring program instruc-tions to said arithmetic logic unit; second means for providing a generated value of N during running of the system; and third means, responsive to a determination by said first means that an N-iterative function will be required by the next program instruction, for jamming the N-value provided by said second means into the system and writing over the N-field input of the arith-metic logic unit.
Claim 5
Dependent Claim 109 words
An adaptive data processing system for performing iterative functions, non-iteratively, said system comprising: an arithmetic logic unit having an N-field input, said arithmetic logic unit including means for executing an N-iterative function directly in a rapid non-iterative manner; first means for monitoring program instruc-tions to said arithmetic logic unit; second means for providing a generated value of N during running of the system; and third means, responsive to a determination by said first means that an N-iterative function will be required by the next program instruction, for jamming the N-value provided by said second means into the system and writing over the N-field input of the arith-metic logic unit.
Claim 6
Dependent Claim 19 words
A system as set forth in Claim 3, wherein said arithmetic logic unit includes a high speed barrel shifter.
Claim 7
Dependent Claim 23 words
A system as set forth in Claim 3, wherein said second means provides a value of N generated by said arithmetic logic unit.
Claim 8
Dependent Claim 26 words
A system as set forth in Claim 3, wherein said second means provides a value of N from a source other than said arithmetic logic unit.
Claim 9
Dependent Claim 23 words
A system as set forth in Claim 3, wherein said first means includes a data multiplexer receiving microcode instructions from a pipeline latch.
Claim 10
Dependent Claim 59 words
A system as set forth in Claim 3, wherein said third means includes a multiplexer which passes N-values through a pipeline latch to said arithmetic logic unit when said multiplexer is enabled by said first means upon detection by said first means of an indication in a preceding programming instruction that the next instruction will call for an N-value.
Claim 11
Dependent Claim 150 words
An adaptive data processing system for performing iterative functions non-iteratively, said system comprising: an arithmetic logic unit having an N-field input, said arithmetic logic unit including barrel shifter means within said arithmetic logic unit for executing an N-iterative function directly in a single cycle rather than by iterative looping; first means for monitoring program instruc-tions to said arithmetic logic unit; second means for providing a generated value of N during running of the system, the value of N being derived from either the output of said arithmetic logic unit or from an external source other than said arithmetic logic unit; and third means including a multiplexer which passes N-values through a pipeline latch to said arithmetic logic unit when said multiplexer is enabled by said first means upon detection by said first means of an indication in a preceding programming instruction that the next instruction will call for an N-value.
Claim 12
Dependent Claim 150 words
An adaptive data processing system for performing iterative functions non-iteratively, said system comprising: an arithmetic logic unit having an N-field input, said arithmetic logic unit including barrel shifter means within said arithmetic logic unit for executing an N-iterative function directly in a single cycle rather than by iterative looping; first means for monitoring program instruc-tions to said arithmetic logic unit; second means for providing a generated value of N during running of the system, the value of N being derived from either the output of said arithmetic logic unit or from an external source other than said arithmetic logic unit; and third means including a multiplexer which passes N-values through a pipeline latch to said arithmetic logic unit when said multiplexer is enabled by said first means upon detection by said first means of an indication in a preceding programming instruction that the next instruction will call for an N-value.
Claim 13
Dependent Claim 23 words
A system as set forth in Claim 9, wherein said first means includes a data multiplexer receiving microcode instructions from a pipeline latch.
Claim 14
Independent Claim 66 words
A method for performing iterative func-tions, non-iteratively, comprising the steps of: monitoring program instructions to a processor having an N-field input; providing a generated value of N during processing; and writing over the N-field input of the pro-cessor with the generated value of N whenever the step of monitoring detects an indication in a preceding program instruction that the next instruction will call for an N-value.
Claim 15
Independent Claim 66 words
A method for performing iterative func-tions, non-iteratively, comprising the steps of: monitoring program instructions to a processor having an N-field input; providing a generated value of N during processing; and writing over the N-field input of the pro-cessor with the generated value of N whenever the step of monitoring detects an indication in a preceding program instruction that the next instruction will call for an N-value.
Claim 16
Independent Claim 120 words
A method for performing iterative func-tions, non-iteratively, comprising the steps of: monitoring program instructions to an arithme-tic logic unit having an N-field input; providing a generated value of N during actual processing, said value of N being derived either from the output of the arithmetic logic unit itself or from some external source other than the arithmetic logic unit; writing over the N-field input of the arith-metic logic unit with the generated value of N whenever the step of monitoring detects an indication in a preceding program instruction that the next instruc-tion will call for an N-value; and executing the N-iterative function directly in a single cycle within the arithmetic logic unit, using said value of N generated during processing.
Claim 17
Independent Claim 120 words
A method for performing iterative func-tions, non-iteratively, comprising the steps of: monitoring program instructions to an arithme-tic logic unit having an N-field input; providing a generated value of N during actual processing, said value of N being derived either from the output of the arithmetic logic unit itself or from some external source other than the arithmetic logic unit; writing over the N-field input of the arith-metic logic unit with the generated value of N whenever the step of monitoring detects an indication in a preceding program instruction that the next instruc-tion will call for an N-value; and executing the N-iterative function directly in a single cycle within the arithmetic logic unit, using said value of N generated during processing.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag