Patent CA1218754A successfully refreshed from Google Patents.
CA1218754A
Expired / Lapsed
CA
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Computer vector multi-processing control
Assignee: Cray Research LLC
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Filing: 1984-04-24
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Granted: 1987-03-03
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Expires: 2004-04-24
Abstract
Abstract Abstract of the Disclosure A multiprocessing system and method for multiprocessing disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory between the CPU. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devi-ces. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multi-tasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and faciliates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
Inventors
- 👤 Steve S. Chen
- 👤 Alan J. Schiffleger
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-10-25 20:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092; G06F9/30076; G06F9/30087; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
244 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; paths select means associated with said vec-tor registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vec-tor registers for transmitting data as operands to a functional unit and for receiving results from a func-tional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, as results from the functional unit become available.
Claim 2
Dependent Claim
244 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; paths select means associated with said vec-tor registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vec-tor registers for transmitting data as operands to a functional unit and for receiving results from a func-tional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, as results from the functional unit become available.
Claim 3
Dependent Claim
296 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a func-tional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector as results from the functional unit become available, said control means further operative to resolve reference conflicts between simultaneously attempted read and write operations to the same memory bank and to cause one of said attempted references to be forced to another memory bank so that subsequent simultaneous read and write operations occur in different ones of said memory banks.
Claim 4
Dependent Claim
296 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a func-tional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector as results from the functional unit become available, said control means further operative to resolve reference conflicts between simultaneously attempted read and write operations to the same memory bank and to cause one of said attempted references to be forced to another memory bank so that subsequent simultaneous read and write operations occur in different ones of said memory banks.
Claim 5
Dependent Claim
281 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including at least two individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a func-tional unit and for receiving results from a functional unit; and control means associated with each of said vector registers and responsive to program instruc-tions, said control means including a vector read control and a vector write control, said vector read control including means for monitoring the availability of operands and producing a data ready signal indica-tive thereof that may be monitored by another vector read control to determine when both are ready to send an operand to a functional unit, said read control further producing a go write signal each time an operand is sent to a functional unit, said go write signal being sent to the functional along with the operand and delayed in the functional unit until the corresponding result is produced thereby and then deli-vered to the vector write control associated with the vector register designated to receive the result to signal said register that a result is to be accepted for writing to a memory bank.
Claim 6
Dependent Claim
281 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including at least two individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an out-put for delivering results, said functional unit including segmented means for holding data for opera-tions not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a func-tional unit and for receiving results from a functional unit; and control means associated with each of said vector registers and responsive to program instruc-tions, said control means including a vector read control and a vector write control, said vector read control including means for monitoring the availability of operands and producing a data ready signal indica-tive thereof that may be monitored by another vector read control to determine when both are ready to send an operand to a functional unit, said read control further producing a go write signal each time an operand is sent to a functional unit, said go write signal being sent to the functional along with the operand and delayed in the functional unit until the corresponding result is produced thereby and then deli-vered to the vector write control associated with the vector register designated to receive the result to signal said register that a result is to be accepted for writing to a memory bank.
References Cited (Backward Citations)
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