USRE32278E
Expired / Lapsed
US
⏱️ 0.0 years remaining
Muting circuit
Assignee: Sony Corp
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Filing: 1985-06-28
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Granted: 1986-11-04
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Expires: 2005-06-28
Abstract
Abstract Disclosed is a muting circuit, in which the generation of click noise is prevented in that the muting operation is caused to occur at an instant when the instantaneous level (i.e., waveform level) of the input audio signal becomes zero for the first time since the appearance of a muting signal. .Iadd.A muting-off circuit is also disclosed for turning off the muting circuit. .Iaddend.
Inventors
- 👤 Teppei Yokota
- 👤 Yoshiro Joichi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:52
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/341
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
111 words
A digital muting circuit comprising, an input terminal .[.for.]. receiving a PCM signal having words of plural bits, an output terminal .[.for.]. deriving said PCM signal, a controlling circuit .[.for.]. generating a muting signal, a detecting circuit for examining the bit pattern of said PCM signal to produce a detected signal when the signal level of the waveform corresponding to said PCM signal is less than a predetermined value, and switching means connected between said input terminal and said output terminal and .[.for.]. replacing said PCM .Iadd.output .Iaddend.signal with a PCM signal having a bit pattern representing the zero level by receiving said detected signal while said muting signal is generated.
Claim 2
Dependent Claim
111 words
A digital muting circuit comprising, an input terminal .[.for.]. receiving a PCM signal having words of plural bits, an output terminal .[.for.]. deriving said PCM signal, a controlling circuit .[.for.]. generating a muting signal, a detecting circuit for examining the bit pattern of said PCM signal to produce a detected signal when the signal level of the waveform corresponding to said PCM signal is less than a predetermined value, and switching means connected between said input terminal and said output terminal and .[.for.]. replacing said PCM .Iadd.output .Iaddend.signal with a PCM signal having a bit pattern representing the zero level by receiving said detected signal while said muting signal is generated.
Claim 3
Dependent Claim
73 words
A digital muting circuit according to claim 1, further comprising time counting means .[.for.]. counting a predetermined time elapsed from the instant of change of said muting signal and .[.for.]. producing a switching signal so as to cause the switching operation of said switching means on the basis of the relationship between the time elapsed from the instant of change of said muting signal and the waveform level of said input signal. .Iadd.
Claim 4
Dependent Claim
177 words
A digital muting circuit comprising, an input terminal receiving a PCM signal having words of plural bits, an output terminal deriving said PCM signal, a controlling circuit generating a muting-off signal, a detecting circuit examining the bit pattern of said PCM signal to produce a detected signal when the signal level of the waveform corresponding to said PCM signal is less than a predetermined value, and switching means connected between said input terminal and said output terminal and replacing a PCM output signal having a bit pattern representing the zero level with said PCM signal by receiving said detected signal when said muting-off signal is generated..Iaddend. .Iadd.4. A digital muting circuit according to claim 3, further comprising time counting means counting a predetermined time elapsed from the instant of change of said muting-off signal and producing a switching signal so as to cause the switching operation of said switching means on the basis of the relationship between the time elapsed from the instant of change of said muting-off signal and the waveform level of said input signal..Iaddend.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-03 | 1990-05-05 | 1990-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-03 | 1994-05-05 | 1994-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-03 | 1998-05-05 | 1998-11-04 | $7700.00 | Window Closed / Lapsed |