Burst-error correcting system

Claim 2

A digital signal transmission system comprising: means for providing a first error correcting signal from generation elements comprised of a plurality of words of digital information; delay means for relatively delaying said plurality of words of digital information so as to have delay times that are different from each other; means for providing a second error correcting signal from a plurality of generation elements comprised of said relatively delayed words and first error correcting signal; and means for transmitting said relatively delayed words of digital information and first and second error correcting signals .Iadd.as serial data sequences, each sequence containing first and second error correcting signals and relatively delayed words of digital information, with any particular one of said error correcting signals and the respective generation elements therefor appearing in different ones of said serial data sequences. .Iaddend.

Claim 3

A digital signal transmission system according to claim 1; in which said means for providing the first error correcting signal includes a modulo-two-adding means.

Claim 4

A digital signal transmission system according to claim 2; in which said means for providing the second error correcting signal includes another modulo-two-adding means.

Claim 5

A digital signal transmission signal according to claim 3; in which said means for providing the second error correcting signal further includes additional delay means for relatively delaying said first error correcting signal in respect to said relatively delayed words of digital information, and said other modulo-two-adding means receives the delayed first error correcting signal and at least one of the relatively delayed words of digital information.

Claim 6

A digital signal transmission system comprising: means acting on a plurality of words of digital information to form a first .[.parity.]. .Iadd.error checking .Iaddend.signal therefrom; first delay means for relatively delaying said words of digital information so as to have delay times that are different from each other; means for providing a second .[.parity.]. .Iadd.error checking .Iaddend.signal from a plurality of generation elements comprised of said relatively delayed words of digital information and said first .[.parity.]. .Iadd.error checking .Iaddend.signal; means for transmitting and receiving said relatively delayed words of digital information and first and second .[.parity.]. .Iadd.error checking .Iaddend.signals; means for providing a first syndrome from a plurality of generation elements comprised of the received first and second .[.parity.]. .Iadd.error checking .Iaddend.signals and words of digital information; second delay means for relatively delaying the received words of digital information in a fashion reverse to that effected by said first delay means; means connected to said second delay meas for providing a second syndrome from generation elements comprised of the words of digital information as relatively delayed by said second delay means and said first .[.parity.]. .Iadd.error checking .Iaddend.signals; detecting means receiving said first and second syndromes for detecting the received words of digital information having an error; and means for correcting the error of the received words of digital information in response to said syndromes.

Claim 7

A digital signal transmission system comprising: means acting on a plurality of words of digital information to form a first .[.parity.]. .Iadd.error checking .Iaddend.signal therefrom; first delay means for relatively delaying said words of digital information so as to have delay times that are different from each other; means for providing a second .[.parity.]. .Iadd.error checking .Iaddend.signal from a plurality of generation elements comprised of said relatively delayed words of digital information and said first .[.parity.]. .Iadd.error checking .Iaddend.signal; means for transmitting and receiving said relatively delayed words of digital information and first and second .[.parity.]. .Iadd.error checking .Iaddend.signals; means for providing a first syndrome from a plurality of generation elements comprised of the received first and second .[.parity.]. .Iadd.error checking .Iaddend.signals and words of digital information; second delay means for relatively delaying the received words of digital information in a fashion reverse to that effected by said first delay means; means connected to said second delay meas for providing a second syndrome from generation elements comprised of the words of digital information as relatively delayed by said second delay means and said first .[.parity.]. .Iadd.error checking .Iaddend.signals; detecting means receiving said first and second syndromes for detecting the received words of digital information having an error; and means for correcting the error of the received words of digital information in response to said syndromes.

Claim 8

A digital signal transmission system according to claim 5; in which .Iadd.said first and second error checking signals are parity signals, and .Iaddend.said means for providing said first and second .[.parity.]. .Iadd.error checking .Iaddend.signals respectively include first and second modulo-two-adders.

Claim 9

A digital signal transmission system according to claim 6; in which said means for providing the second parity signal further includes third delay means for relatively delaying said first parity signal in respect to said relatively delayed word of digital information and said second modulo-two-adder receives the delayed first parity signal and at least one of the relatively delayed words of digital information.

Claim 10

A digital signal transmission system according to claim 6; in which said means for providing said first and second syndromes respectively include third and fourth modulo-two-adders.

Claim 11

A digital signal transmission system according to claim 8; in which said relatively delayed words of digital information and said first and second parity signals are serially transmitted and received.

Claim 12

A digital signal transmission system according to claim 8, in which said detecting means includes comparing means for comparing the outputs of said third and fourth modulo-two-adders, and providing an error signal as an output of the comparing means.

Claim 13

A digital signal transmission system according to claim 10, in which said correcting means includes a fifth modulo-two-adder for adding said error signal with the output of one of said third and fourth modulo-two-adders.

Claim 14

In apparatus for reproducing a .[.recorded.]. .Iadd.transmitted .Iaddend.digital signal comprised of words of digital information which are relatively delayed to have .Iadd.delay .Iaddend.times different from each other, a first .[.parity.]. .Iadd.error checking .Iaddend.signal generated from generation elements comprised of said words of digital information, and a second .[.parity.]. .Iadd.error checking .Iaddend.signal generated from a plurality of generation elements comprised of said relatively delayed words and first .[.parity.]. .Iadd.error checking .Iaddend.signal; a .[.reproduced.]. .Iadd.reproducing .Iaddend.signal processing circuit comprising: means for providing a first syndrome from a plurality of generation elements comprised of the reproduced words of digital information and first and second .[.parity.]. .Iadd.error checking .Iaddend.signals; delay means for relatively delaying the reproduced words of digital information in a fashion reverse to that with which said words were .[.recorded.]. .Iadd.relatively delayed for transmission; .Iaddend. means connected to said delay means for providing a second syndrome from generation elements comprised of the reproduced words of digital information as relatively delayed by said delay means and said first .[.parity.]. .Iadd.error checking .Iaddend.signal; detecting means .[.receiving said frist and second syndromes.]. for detecting .[.therefrom.]. those reproduced words of digital information having .[.an.]. .Iadd.at least one word .Iaddend.error; and; means for correcting a detected .Iadd.at least one word .Iaddend.error in the reproduced words of digital information .[.in response to said syndromes.]. .Iadd.with said first and second syndrome in response to a corresponding output from said detecting means. .Iaddend.

Claim 15

In apparatus for reproducing a .[.recorded.]. .Iadd.transmitted .Iaddend.digital signal comprised of words of digital information which are relatively delayed to have .Iadd.delay .Iaddend.times different from each other, a first .[.parity.]. .Iadd.error checking .Iaddend.signal generated from generation elements comprised of said words of digital information, and a second .[.parity.]. .Iadd.error checking .Iaddend.signal generated from a plurality of generation elements comprised of said relatively delayed words and first .[.parity.]. .Iadd.error checking .Iaddend.signal; a .[.reproduced.]. .Iadd.reproducing .Iaddend.signal processing circuit comprising: means for providing a first syndrome from a plurality of generation elements comprised of the reproduced words of digital information and first and second .[.parity.]. .Iadd.error checking .Iaddend.signals; delay means for relatively delaying the reproduced words of digital information in a fashion reverse to that with which said words were .[.recorded.]. .Iadd.relatively delayed for transmission; .Iaddend. means connected to said delay means for providing a second syndrome from generation elements comprised of the reproduced words of digital information as relatively delayed by said delay means and said first .[.parity.]. .Iadd.error checking .Iaddend.signal; detecting means .[.receiving said frist and second syndromes.]. for detecting .[.therefrom.]. those reproduced words of digital information having .[.an.]. .Iadd.at least one word .Iaddend.error; and; means for correcting a detected .Iadd.at least one word .Iaddend.error in the reproduced words of digital information .[.in response to said syndromes.]. .Iadd.with said first and second syndrome in response to a corresponding output from said detecting means. .Iaddend.

Claim 16

The apparatus according to claim 12; in which .Iadd.said first and second error checking signals are respectively first and second parity signals, .Iaddend.said first parity signal is a modulo-two summation of said words of digital information and said second parity signal is a modulo-two summation of said first parity signal and at least one of the relatively delayed words of digital information; and in which said means for providing said first and second syndromes includes first and second modulo-two-adders, respectively.

Claim 17

The apparatus according to claim 13; in which said detecting means includes comparing means for comparing the outputs of said first and second modulo-two-adders and providing an error signal as an output of the comparing means.

Claim 18

The apparatus according to claim 14; in which said means for correcting includes an additional modulo-two-adder for adding said error signal to the output of one of said first and second adders.

Claim 19

A digital signal transmission system comprising: means for providing a plurality of words of digital information; means for arranging said words of digital information in a first state of arrangement; means for providing a first error correcting signal from generation elements comprised of said words of digital information in said first state; delay means for relatively delaying said plurality of words of digital information so as to have delay times that are different from each other, and for arranging the words of digital information in a second state of arrangement; means for providing a second error correcting signal from a plurality of generation elements comprised of said relatively delayed words and first error correcting signal; and means for transmitting said words of digital information and first and second error correcting signals .Iadd.as serial data sequences, each sequence containing first and second error correcting signals and relatively delayed words of digital information, with any particular one of said error correcting signals and the respective generation elements therefor appearing in different ones of said serial data sequences.Iaddend..

Claim 20

A digital signal transmission system comprising: means for providing a plurality of words of digital information; means for arranging said words of digital information in a first state of arrangement; means for providing a first error correcting signal from generation elements comprised of said words of digital information in said first state; delay means for relatively delaying said plurality of words of digital information so as to have delay times that are different from each other, and for arranging the words of digital information in a second state of arrangement; means for providing a second error correcting signal from a plurality of generation elements comprised of said relatively delayed words and first error correcting signal; and means for transmitting said words of digital information and first and second error correcting signals .Iadd.as serial data sequences, each sequence containing first and second error correcting signals and relatively delayed words of digital information, with any particular one of said error correcting signals and the respective generation elements therefor appearing in different ones of said serial data sequences.Iaddend..

Claim 21

A digital signal transmission system according to claim 16; further comprising: means for receiving the transmitted words of digital information and first and second error correcting signals; means for rearranging the received words of digital information into said second state; means for providing a first syndrome from a plurality of generation elements comprised of the first and second error correcting signals and the rearranged words of digital information in said second state; means for arranging the received words of digital information into said first state; means for providing a second syndrome from said first error correcting signal and the rearranged words of digital information in said first state; detecting means receiving said first and second syndromes for detecting the received words of digital information having an error; and means for correcting the error of the received words of digital information in response to said syndromes.

Claim 22

A carrier storing digital information comprised of words of digital information, a first .[.parity.]. .Iadd.error checking .Iaddend.signal having said words of digital information as its generation elements and a second .[.parity.]. .Iadd.error checking .Iaddend.signal formed of a plurality of generation elements comprised of said words and first .[.parity.]. .Iadd.error checking .Iaddend.signal which are relatively delayed .[.to have times.]. .Iadd.by .Iaddend.different .Iadd.times .Iaddend.from each other .Iadd., said words of digital information and said error checking signals being stored as serial data sequences each containing first and second error checking signals and relatively delayed words of digital information with said error correcting signals and the respective generation elements appearing in different ones of said serial data sequences.Iaddend.. .Iadd. 19. The apparatus according to claim 12; in which said first error checking signal is additionally delayed with respect to said relatively delayed words of digital information. .Iaddend.