Process for forming interconnections in a multilayer circuit board

Claim 2

A process for forming electrical connections between circuit layers of a multilayer board, said process comprising the steps of, producing a circuit pattern on at least one surface of an insulating substrate, covering said circuit pattern and said one surface with a thin conducting layer, disposing a reusable mask over said thin conducting layer, said mask having a pattern of openings defining locations for electrical connections to said circuit pattern, filling said openings with a conducting material to form conducting members on said circuit pattern, removing said reusable mask and the portion of said thin conducting layer on said one surface, applying an insulating layer over the surface of said insulating substrate and around said conducting members, the surface of said insulating layer and the tops of said conducting members being in approximately the same plane, producing a second circuit pattern on the surface of said insulating layer, said circuit pattern having portions connected to at least certain of said conducting members.

Claim 3

The process as recited in claim 1, including the steps of, covering said second circuit pattern and the surface of said insulating layer with a second thin conducting layer, disposing said reusable mask over the surface of said second thin conducting layer, said mask having a pattern of openings defining locations for electrical connections to said second conductor pattern, filling said openings with a conducting material to form second conducting members on said second circuit pattern, removing said reusable mask and the portions of said second thin conducting layer on said insulating layer, applying an insulating layer on the surface of said first recited insulating layer and around said second conducting members, the surface of said second recited insulating layer and the tops of said second conducting members being in approximately the same plane, forming a third circuit pattern on the surface of said second recited insulating layer, said circuit pattern having portions connected to at least certain of said second conducting members. .Iadd. 3. A method of fabricating an individual layer of a multilayer printed circuit board, comprising the steps of: forming a printed circuit on an insulator substrate; coating said printed circuit with a thin conductive layer of material; conforming an apertured masking material to said conductive layer on said printed circuit on said insulator substrate; said masking material including apertures therein in the desired pattern of at least one interlayer connector; electroforming said connector using said conductive layer as an electrical path in the electroforming operation; removing the masking material and the resultant exposed material of the conductive layer; and insulating the printed circuit and the interlayer connector, leaving an exposed surface at the end of said interlayer connector. .Iaddend.