Transistor matrix

Abstract

Abstract 14. A TRANSISTOR MATRIX COMPRISING: A PLURALITY OF TRANSISTORS IN A MONOLITHIC INTEGRATED CIRCUIT STRUCTURE, EACH TRANSISTOR HAVING A COLLECTOR PORTION, A BASE PORTION, AND AN EMITTER PORTION, AND INPUT TERMINALS SEPARATELY CONNECTED TO SAID EMITTER PORTIONS AND BASE PORTIONS RESPECTIVELY, EACH TRANSISTOR PROVIDING A COLLECTOR OUTPUT WHEN BOTH INPUT TERMINALS THEREOF RECEIVE A PREDETERMINED INPUT. PLURAL ADJACENT COLLECTOR REGIONS IN SAID MONOLITHIC INTEGRATED CIRCUIT STRUCTURE, SAID COLLECTOR REGIONS BEING PROVIDED BY ADJACENT ISOLATION REGIONS IN A SEMICONDUCTOR LAYER OF SAID MONOLITHIC INTEGRATED CIRCUIT STRUCTURE, WHEREIN COLLECTOR PORTIONS OF ONES OF SAID TRANSISTORS FORM A PART OF THE SAME COLLECTOR REGION, WHILE COLLECTOR PORTIONS OF OTHER ONES OF SAID TRANSISTORS FORM A PART OF OTHER COLLECTOR REGIONS, ONES OF SAID BASE PORTIONS BEING DISPOSED ALONG SAID ISOLATION REGIONS TO PROVIDE ONE OR MORE TRANSISTORS ALONG EACH SUCH ISOLATION REGION WHEREIN A BASE PORTION SEPARATES AN EMITTER PORTION FROM THE CORRESPONDING COLLECTOR REGION, MEANS INTERCONNECTING THE EMITTER INPUT TERMINALS OF SAID TRANSISTORS IN FIRST GROUPS CORRESPONDING RESPECTIVELY TO FIRST INPUT VALUES, SAID MEANS INTERCONNECTING AID EMITTER INPUT TERMINALS COMPRISING FIRST CONDUCTORS INSULATABLY CROSSING SAID ISOLATION REGIONS AND MAKING CONNECTION ONLY WITH EMITTER INPUT TERMINALS OF TRANSISTORS IN THE CORRESPONDING GROUPS, WHEREIN EACH FIRST CONDUCTOR CONNECTS EMITTER INPUT TERMINALS OF NOT MORE THAN ONE TRANSISTOR PER ISOLATION REGION, AND MEANS INTERCONNECTING THE BASE INPUT TERMINALS OF SAID TRANSISTORS IN SECOND GROUPS CORRESPONDING RESPECTIVELY TO SECOND INPUT VALUES, EACH TRANSISTOR BEING IDENTIFIED BY A UNIQUE COMBINATION OF INPUT CONNECTIONS WITH RESPECT TO SAID FIRST AND SECOND GROUPS, SAID MEANS FOR INTERCONNECTING SAID BASE TERMINALS IN SECOND GROUPS COMPRISING SECOND CONDUCTORS DISPOSED IN BETWEEN SAID FIRST CONDUCTORS AND CONNECTING A BASE INPUT TERMINAL DISPOSED IN ONE ISOLATION REGION WITH A BASE INPUT TERMINAL IN THE NEXT ADJACENT ISOLATION REGION OF A TRANSISTOR THE EMITTER OF WHICH IS CONNECTED IN A DIFFERENT FIRST GROUP BY A DIFFERENT FIRST CONDUCTOR, AT LEAST ONES OF SAID BASE PORTIONS BEING PROVIDED WITH A PAIR OF BASE TERMINALS, ONE ON EACH SIDE OF AN EMITTER PORTION, AND TO WHICH SAID SECOND CONDUCTORS ARE CONNECTED IN ORDER THAT SAID SECOND CONDUCTORS MAY BE LOCATED IN BETWEEN FIRST CONDUCTORS WITHOUT CROSSING FIRST CONDUCTORS.

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