USH967H
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed, long distance, data transmission multiplexing circuit
Assignee: United States Department of Energy
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Filing: 1990-01-30
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Granted: 1991-09-03
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Expires: 2010-01-30
Abstract
Abstract A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.
Inventors
- 👤 Razvan Mariotti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:48
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04J3/1682
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
295 words
A circuit for digital data capture at high speed, serial data transmission and multiplexing over long distance and for selecting and continously displaying real time analog signals, comprising; a plurality of data sampling A/D converting, encoding, framing and transmitting modules (1), a plurality of data sampling A/D converting, TDM encoding, framing and transmitting modules (2) for generating character frames for serial synchronous data transmission, a plurality of electric/optic Serial interfaces (3) each of which is operatively connected, respectively, to one of said modules (1 or 2), a plurality of optic/electric interfaces each of which is operatively connected by a fiber-optic data transmission means to one of said electric/optic interfaces, for electrical and optical line communication between said interfaces, a high speed digital multiplexer cross point switch module (5), a plurality of receiver sequencer/decoder and D/A converter circuits (7) each of which include a state machine (11) and is computer programmable, said multiplexing module (5) being made non-blocking and remotely configurable by predetermined computer program signal input from an operator console (6), whereby any input signal received by the multiplexing module can be selectively received and displayed at a display console (7A), and whereby the same input signal can be selected and displayed at the same time at different display consoles (7A/1-4) of said console; each of said sequencer/decoder and D/A circuits (7) being effective to use character frames of the captured data that is transmitted to it in order to detect the data characters and to synchronize such detection, and each of said receiver sequencer/decoder circuits also being made fault tolerant by a "flywheel" algorithm (Appendix C) that is programmed to tolerate one transmission error before the state machine of the sequencer/decoder circuit (4) is out of synchronization for decoding of the said transmitted frames.
Claim 2
Dependent Claim
295 words
A circuit for digital data capture at high speed, serial data transmission and multiplexing over long distance and for selecting and continously displaying real time analog signals, comprising; a plurality of data sampling A/D converting, encoding, framing and transmitting modules (1), a plurality of data sampling A/D converting, TDM encoding, framing and transmitting modules (2) for generating character frames for serial synchronous data transmission, a plurality of electric/optic Serial interfaces (3) each of which is operatively connected, respectively, to one of said modules (1 or 2), a plurality of optic/electric interfaces each of which is operatively connected by a fiber-optic data transmission means to one of said electric/optic interfaces, for electrical and optical line communication between said interfaces, a high speed digital multiplexer cross point switch module (5), a plurality of receiver sequencer/decoder and D/A converter circuits (7) each of which include a state machine (11) and is computer programmable, said multiplexing module (5) being made non-blocking and remotely configurable by predetermined computer program signal input from an operator console (6), whereby any input signal received by the multiplexing module can be selectively received and displayed at a display console (7A), and whereby the same input signal can be selected and displayed at the same time at different display consoles (7A/1-4) of said console; each of said sequencer/decoder and D/A circuits (7) being effective to use character frames of the captured data that is transmitted to it in order to detect the data characters and to synchronize such detection, and each of said receiver sequencer/decoder circuits also being made fault tolerant by a "flywheel" algorithm (Appendix C) that is programmed to tolerate one transmission error before the state machine of the sequencer/decoder circuit (4) is out of synchronization for decoding of the said transmitted frames.
Claim 3
Dependent Claim
45 words
An invention as defined in claim 1 wherein said high speed digital multiplexer module (5) is controlled by an operator using the operator console (6) to selectively route certain of the captured data input signals to given desired outputs of the receiver sequencer/decoder circuits (7).
Claim 4
Dependent Claim
109 words
An invention as defined in claim 1 wherein each of said A/D converting, encoding and framing modules (1) is operable to sample captured data at a rate of 1 Mhz and to transmit analog signals in the range 0 to 100 Khz in which each transmitted frame is made to consist of 15 bits, and wherein each said A/D converting modules (2) is provided with four channel time division multiplexing (TDM) mode of transmission and is operable to sample at a rate of 200 Khz and to transmit analog signals in the range 0 to 20 Khz in which each transmitted frame is made to consist of 18 bits.
Claim 5
Dependent Claim
50 words
An invention as defined in claim 3 wherein the first frame bit is made the "start" bit, the last bit is made the "stop" bit, and a predetermined one of the intermediate bits is made a "type" bit, in each frame of both the TDM and non-TDM mode of transmission.
Claim 6
Dependent Claim
21 words
An invention as defined in claim 4 wherein the second bit in each of said frames is made the "type" bit.
Claim 7
Dependent Claim
51 words
An invention as defined in claim 4 wherein each of said modules (1 and 2) are operable to prevent locking of said receiver sequencer/decoder (7) by toggling the "stop" bit on each frame transmitted to it, whereby the receiving of each frame is synchronized for detection by this receiver sequencer/decoder (7).
Claim 8
Dependent Claim
37 words
An invention as defined in claim 3 wherein said circuit (1) is operable to transmit signals at 1 Mhz sampling rate with 12 bits accuracy and with 3 bits overhead for framing in non-TDM mode of transmission.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |