Patent US3416701A successfully refreshed from Google Patents.
USH512H
Expired / Lapsed
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Automated universal array
Assignee: United States Department of the Army
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Filing: 1986-02-18
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Granted: 1988-08-02
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Expires: 2006-02-18
Abstract
Abstract A large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing. Interconnection and vertical signal routing between cell rows can be made through a feedthrough in each internal cell and connection to selective vertical tunnels without touching the overhead horizontal wiring channels which provide horizontal signal routing. A side peripheral roadbed area adjoins the cell rows and inner roadbed area and consists of an alternating pattern of horizontal and vertical tunnels which permit interfacing with a bordering arrangement of peripheral cells consisting of basic peripheral cells and special purpose cells as well as providing coupling to a pair of common power busses which are located on the outer perimeter of the array.
Inventors
- 👤 Fred Borgini
- 👤 Richard Noto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
457 words
A universal array of active and passive circuit components formed on a semiconductor chip and adapted for single level interconnection to provide a desired circuit implementation, comprising in combination: plural first direction rows of identical symmetrical inner cells of uncommitted circuit components; a bordering configuration of peripheral cells for providing an off-chip interface; a first roadbed area on each side of said plural rows of inner cells, said first roadbed area having a second direction tunnel pattern including at least three sets of plural parallel conductive tunnels mutually spaced apart in said second direction for permitting first and second type interconnections between adjacent tunnel sets for second direction signal routing within the array and having respective predetermined conductive tunnel lengths permitting plural parallel first direction conductive wiring channels crossing thereover for first direction signal routing within the array; a second roadbed area at each end of said plural rows of inner cells as well as said first roadbed area, said second roadbed area having a first direction tunnel pattern adjacent each first roadbed area and including a set of plural parallel first direction conductive tunnels and having respective predetermined tunnel lengths permitting plural parallel second direction conductive wiring channels crossing thereover for second direction signal routing within the array, and a second direction tunnel pattern adjacent each row of inner cells and aligned with said first direction tunnel pattern and including a set of plural parallel second direction conductive tunnels for selective connection of said second direction conductive channels of said first direction tunnel pattern and having respective predetermined tunnel lengths permitting at least one first direction conductive wiring channel crossing thereover; and a pair of peripheral power busses connecting opposite polarity potentials to said plurality of inner and peripheral cells, said power busses running parallel and spaced across said peripheral cells around four sides of said array and including a plurality of branch busses in said first direction connected to respective power busses and crossing over said second direction tunnel pattern adjacent each row of inner cells and running through said array for applying said opposite polarity potentials to said plural first direction rows of inner cells, a pair of bonding pads at one corner for connecting an external power source to respective said power busses, and a bridge over one power buss for connecting the other power buss to one bonding pad while maintaining separation from the one buss and the other bonding pad, said peripheral cells each including a plurality of tunnels crossing under one said power buss and providing connections between said peripheral cells and inner cells, a further bonding pad for connection to external circuit means, and a pair of high impedance devices connected between said power busses and said peripheral cells.
Claim 2
Dependent Claim
457 words
A universal array of active and passive circuit components formed on a semiconductor chip and adapted for single level interconnection to provide a desired circuit implementation, comprising in combination: plural first direction rows of identical symmetrical inner cells of uncommitted circuit components; a bordering configuration of peripheral cells for providing an off-chip interface; a first roadbed area on each side of said plural rows of inner cells, said first roadbed area having a second direction tunnel pattern including at least three sets of plural parallel conductive tunnels mutually spaced apart in said second direction for permitting first and second type interconnections between adjacent tunnel sets for second direction signal routing within the array and having respective predetermined conductive tunnel lengths permitting plural parallel first direction conductive wiring channels crossing thereover for first direction signal routing within the array; a second roadbed area at each end of said plural rows of inner cells as well as said first roadbed area, said second roadbed area having a first direction tunnel pattern adjacent each first roadbed area and including a set of plural parallel first direction conductive tunnels and having respective predetermined tunnel lengths permitting plural parallel second direction conductive wiring channels crossing thereover for second direction signal routing within the array, and a second direction tunnel pattern adjacent each row of inner cells and aligned with said first direction tunnel pattern and including a set of plural parallel second direction conductive tunnels for selective connection of said second direction conductive channels of said first direction tunnel pattern and having respective predetermined tunnel lengths permitting at least one first direction conductive wiring channel crossing thereover; and a pair of peripheral power busses connecting opposite polarity potentials to said plurality of inner and peripheral cells, said power busses running parallel and spaced across said peripheral cells around four sides of said array and including a plurality of branch busses in said first direction connected to respective power busses and crossing over said second direction tunnel pattern adjacent each row of inner cells and running through said array for applying said opposite polarity potentials to said plural first direction rows of inner cells, a pair of bonding pads at one corner for connecting an external power source to respective said power busses, and a bridge over one power buss for connecting the other power buss to one bonding pad while maintaining separation from the one buss and the other bonding pad, said peripheral cells each including a plurality of tunnels crossing under one said power buss and providing connections between said peripheral cells and inner cells, a further bonding pad for connection to external circuit means, and a pair of high impedance devices connected between said power busses and said peripheral cells.
Claim 3
Dependent Claim
24 words
The universal array as defined by claim 1 wherein said first direction comprises the horizontal direction and said second direction comprises the vertical direction.
Claim 4
Dependent Claim
29 words
The universal array as defined by claim 1 wherein said first roadbed area between rows of cells consists of a tunnel pattern including five sets of second direction tunnels.
Claim 5
Dependent Claim
23 words
The universal array as defined by claim 3 wherein the second direction spacing between said five sets of conductive tunnels is substantially equal.
Claim 6
Dependent Claim
20 words
The universal array as defined by claim 4 wherein second direction spacing is less than the respective predetermined tunnel lengths.
Claim 7
Dependent Claim
23 words
The universal array as defined by claim 5 wherein the respective tunnel lengths of said five sets of conductive tunnels are substantially equal.
Claim 8
Dependent Claim
30 words
The universal array as defined by claim 6 wherein the widths of the individual tunnels of said five sets of tunnels are substantially equal and less than their respective lengths.
Claim 9
Dependent Claim
38 words
The universal array as defined by claim 6 wherein the lengths of said conductive tunnels of said second direction pattern of said second roadbed area are substantially equal to the tunnel lengths of said five sets of conductive
Claim 10
Dependent Claim
46 words
The universal array as defined by claim 8 wherein the widths of the conductive tunnels of said first direction tunnel pattern of said second roadbed area are greater than the widths of the conductive tunnels of said second direction tunnel pattern of said second roadbed area.
Claim 11
Dependent Claim
48 words
The universal array as defined by claim 1 wherein each cell of said plural rows of cells laterally spans an equal number of second direction conductive tunnels of one of said at least three sets of tunnels of said first roadbed area on opposite sides of said cell.
Claim 12
Dependent Claim
51 words
The universal array as defined by claim 10 wherein each of said equal number of second direction conductive tunnels terminates in a respective pair of conductive contact pads or pins, one of which is located adjacent said cell and one of which is located a tunnel length away from said cell.
Claim 13
Dependent Claim
28 words
The universal array as defined by claim 11 wherein each cell includes a feedthrough conductive tunnel connected to one adjacent contact pad on opposite sides of said cell.
Claim 14
Dependent Claim
40 words
The universal array as defined by claim 11 wherein each cell comprises a plurality of active semiconductor devices for implementing a logic gate, said devices respectively having an input terminal coupled to individual contact pads of said adjacent contact pads.
Claim 15
Dependent Claim
49 words
The universal array as defined by claim 13 wherein each said cell includes four semiconductor devices two of which are located on respective opposite halves of said cell and wherein said four devices have respective input terminals coupled to two individual contact pads on opposite sides of said cell.
Claim 16
Dependent Claim
14 words
The universal array as defined by claim 14 wherein said semiconductor devices comprise transistors.
Claim 17
Dependent Claim
24 words
The universal array as defined by claim 15 wherein said two transistors on opposite halves of said cell are respectively of opposite semiconductivity type.
Claim 18
Dependent Claim
24 words
The universal array as defined by claim 15 wherein two of said transistors comprise N-type transistors and two of said transistors comprise P-type transistors.
Claim 19
Dependent Claim
29 words
The universal array as defined by claim 15 wherein said transistors include gate, drain and source diffusion regions and wherein said gate regions are common to said input terminals.
Claim 20
Dependent Claim
83 words
The universal array as defined by claim 14 wherein said equal number of second direction conductive tunnels comprise five conductive tunnels on opposite sides of said cell and wherein said respective input terminals are coupled via respective polysilicon tunnels to two individual contact pads of said five tunnels on opposite sides of said cell and wherein said cell additionally includes a polysilicon feedthrough conductive tunnel connected at opposite ends to another contact pad of said five tunnels on opposite sides of said cell.
Claim 21
Dependent Claim
54 words
The universal array as defined by claim 19 wherein said semiconductor devices comprise three terminal devices one of which comprises said input terminal and wherein the two remaining terminals are adapted to be selectively coupled via metals interconnects to the remaining contact pads of said five conductive tunnels on opposite sides of said cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |