Signal processing

Claim 3

The method of claim 1 , comprising digitizing the analog signal at a sampling rate R=4*3*F c =12F c or R=4*3*5*F c =60F c .

Claim 4

The method of claim 1 , wherein digitizing the analog signal is performed using pulse-density modulation (PDM) or pulse-width modulation (PWM).

Claim 5

The method of claim 1 , wherein digitizing the analog signal comprises carrying out delta-sigma modulation to produce a one-bit input bit stream.

Claim 6

The method of claim 1 , wherein digitizing the analog signal is performed using pulse-code modulation (PCM).

Claim 7

The method of claim 1 , wherein digitizing the analog signal comprises carrying out multi-bit conversion to produce a multi-bit input bit stream.

Claim 8

The method of claim 1 , comprising generating a multi-bit in-phase reference bit stream that is synchronous to the carrier frequency F c .

Claim 9

The method of claim 1 , further comprising: generating a quadrature reference bit stream that is synchronous to the carrier frequency F c and represents a quadrature digital reference signal substantially in the form of a cosine and/or sine wave; and multiplying the input bit stream with the quadrature reference bit stream to produce an output bit stream representing a quadrature component of the analog signal.

Claim 10

The method of claim 8 , comprising generating a pair of synchronous in-phase and quadrature reference bit streams.

Claim 11

The method of claim 1 , wherein generating an in-phase reference bit stream that is synchronous to the carrier frequency F c comprises controlling a clock so as to skew the timing to achieve phase accuracy.

Claim 12

A pickoff signal processing system for a sensor comprising a movement sensing structure, the system comprising: an analog-to-digital converter (ADC) arranged to digitize an amplitude-modulated analog pickoff signal representing movement of the sensing structure which is at a carrier frequency F c and produce an input bit stream that represents the amplitude of the analog pickoff signal, wherein the ADC is arranged to digitize the analog pickoff signal at a sampling rate R that is synchronous to the carrier frequency F c according to R=2*(1*3*5 . . . N)*F c or R=4*(1*3*5 . . . N)*F c , where N>1 is an odd number representing odd harmonics in the analog signal; a synchronous modulator or look-up table arranged to generate an in-phase reference bit stream that is synchronous to the carrier frequency F c and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and logic means arranged to multiply the input bit stream with the in-phase reference bit stream and produce an output bit stream representing the amplitude modulation of the analog pickoff signal.

Claim 13

A pickoff signal processing system for a sensor comprising a movement sensing structure, the system comprising: an analog-to-digital converter (ADC) arranged to digitize an amplitude-modulated analog pickoff signal representing movement of the sensing structure which is at a carrier frequency F c and produce an input bit stream that represents the amplitude of the analog pickoff signal, wherein the ADC is arranged to digitize the analog pickoff signal at a sampling rate R that is synchronous to the carrier frequency F c according to R=2*(1*3*5 . . . N)*F c or R=4*(1*3*5 . . . N)*F c , where N>1 is an odd number representing odd harmonics in the analog signal; a synchronous modulator or look-up table arranged to generate an in-phase reference bit stream that is synchronous to the carrier frequency F c and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and logic means arranged to multiply the input bit stream with the in-phase reference bit stream and produce an output bit stream representing the amplitude modulation of the analog pickoff signal.

Claim 14

The system of claim 11 , wherein the ADC is arranged to digitize the analog pickoff signal at a sampling rate R=4*3*F c =12F c or R=4*3*5*F c =60F c .

Claim 15

The system of claim 11 , wherein the ADC is arranged to digitize the analog pickoff signal using pulse-density modulation (PDM), or pulse-width modulation (PWM), or pulse-code modulation (PCM).

Claim 16

The system of claim 11 , wherein the ADC is arranged to carry out delta-sigma modulation to produce a one-bit input bit stream.

Claim 17

The system of claim 11 , wherein the ADC is arranged to carry out multi-bit conversion to produce a multi-bit input bit stream.

Claim 18

The system of claim 11 , wherein: the synchronous modulator or look-up table is arranged to generate a quadrature reference bit stream that is synchronous to the carrier frequency F c and represents a quadrature digital reference signal substantially in the form of a cosine and/or sine wave; and the logic means is arranged to multiply the input bit stream with the quadrature reference bit stream to produce an output bit stream representing a quadrature component of the analog signal.

Claim 19

The system of claim 16 , wherein the synchronous modulator or look-up table is arranged to generate a synchronous pair of in-phase and quadrature reference bit streams.

Claim 20

The system of claim 11 , wherein the synchronous modulator or look-up table utilizes a clock controlled relative to the ADC so as to skew the timing to achieve phase accuracy.