US7746140B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scannable latch
Assignee: Twitter Inc
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Filing: 2006-10-19
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Granted: 2010-06-29
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Expires: 2026-10-19
Abstract
Abstract A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
Inventors
- 👤 Sang Hoo Dhong
- 👤 Joel A. Silberman
- 👤 Osamu Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:07
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
57 words
A scannable latch comprising: a dynamic circuit; a first latch for providing a data out signal from a data in signal; and a second latch having two NAND gates coupled to said dynamic circuit and a pair of transfer gates coupled to said two NAND gates for providing a scan out signal from a scan input signal.
Claim 2
Dependent Claim
57 words
A scannable latch comprising: a dynamic circuit; a first latch for providing a data out signal from a data in signal; and a second latch having two NAND gates coupled to said dynamic circuit and a pair of transfer gates coupled to said two NAND gates for providing a scan out signal from a scan input signal.
Claim 3
Dependent Claim
19 words
The scannable latch of claim 1 , wherein said dynamic circuit includes a precharge transistor and a pull-down network.
Claim 4
Dependent Claim
65 words
The scannable latch of claim 1 , wherein an output of a first one of said two NAND gates is connected to a first input of a second one of said two NAND gates, and an output of said second one of said two NAND gates is connected to a first input of said first one of said two NAND gates during a normal mode.
Claim 5
Dependent Claim
32 words
The scannable latch of claim 3 , wherein said two NAND gates become inverters when second inputs of said two NAND gates are held at a logic high during a scan mode.
Claim 6
Dependent Claim
23 words
The scannable latch of claim 1 , wherein said scannable latch generates an output at said first one of said two NAND gates.
Claim 7
Dependent Claim
23 words
The scannable latch of claim 1 , wherein said scan input signal is provided to said transfer gates via an L 1 latch.
Claim 8
Dependent Claim
18 words
The scannable latch of claim 1 , wherein said transfer gates are being toggled during a scan mode.
References Cited (Backward Citations)
US4797838A
Cited
US5272397A
Cited
US5870411A
Cited
US6201415B1
Cited
US6925590B2
Cited
US20030226077A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2013-06-28 | 2013-12-28 | 2014-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2017-06-28 | 2017-12-28 | 2018-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2021-06-28 | 2021-12-28 | 2022-06-29 | $7700.00 | Window Closed / Lapsed |