Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
169 words
A method for reducing power consumption of a cache, the cache adapted for use with a processor, the method comprising: requesting at least a portion of the cache to enter a low-power mode, the cache comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data stored in the corresponding data entry; archiving in a tag archive area, in response to the requesting, particular tags stored in at least some of the tag entries; reducing, in response to the requesting, power provided to at least some of the data entries; repopulating, after the act of reducing power, a subset of the tag entries from the tag archive area; and wherein the cache and the processor are implemented within one or more integrated circuits.
Claim 2
Independent Claim
169 words
A method for reducing power consumption of a cache, the cache adapted for use with a processor, the method comprising: requesting at least a portion of the cache to enter a low-power mode, the cache comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data stored in the corresponding data entry; archiving in a tag archive area, in response to the requesting, particular tags stored in at least some of the tag entries; reducing, in response to the requesting, power provided to at least some of the data entries; repopulating, after the act of reducing power, a subset of the tag entries from the tag archive area; and wherein the cache and the processor are implemented within one or more integrated circuits.
Claim 3
Dependent Claim
31 words
The method of claim 1 , wherein the cache is a multi-way, set-associative cache, and the portion of the cache comprises data portions of one or more ways of the cache.
Claim 4
Dependent Claim
16 words
The method of claim 1 , further comprising the processor accessing the cache during the archiving.
Claim 5
Dependent Claim
16 words
The method of claim 1 , further comprising the processor accessing the cache during the repopulating.
Claim 6
Dependent Claim
44 words
The method of claim 4 , wherein the cache is a multi-way, set-associative cache; and wherein the repopulating comprises restoring into a particular set of the cache, and the restoring into the particular set stops once all ways of the particular set are valid.
Claim 7
Dependent Claim
20 words
The method of claim 1 , further comprising, prior to the repopulating, marking all of the tag entries as invalid.
Claim 8
Dependent Claim
30 words
The method of claim 1 , wherein an order of the repopulating is determined based, at least in part, on a respective likely-to-be-used-soon indicator of each of the particular tags.
Claim 9
Dependent Claim
57 words
The method of claim 7 , wherein the likely-to-be-used-soon indicators are determined based, at least in part, on one or more of software control, recentness of loading of the data entries, and loading of the data entries in response to misses in the cache due to accesses of the processor within a time interval after the repopulating.
Claim 10
Dependent Claim
26 words
The method of claim 1 , further comprising re-fetching into at least some of the data entries having correspondence with the subset of the tag entries.
Claim 11
Dependent Claim
15 words
The method of claim 9 , wherein the re-fetching is in accordance with cache coherency.
Claim 12
Dependent Claim
22 words
The method of claim 9 , wherein the re-fetching is in accordance with cache coherency state archived in the tag archive area.
Claim 13
Dependent Claim
50 words
The method of claim 9 , wherein the cache is a higher-level cache; wherein a lower-level cache adapted for use with the processor is coupled to the higher-level cache; wherein the re-fetching is a higher-level re-fetching; and further comprising, subsequent to the higher-level re-fetching, lower-level re-fetching into the lower-level cache.
Claim 14
Dependent Claim
16 words
The method of claim 9 , further comprising the processor accessing the cache during the re-fetching.
Claim 15
Dependent Claim
45 words
The method of claim 1 , further comprising requesting the at least a portion of the cache to exit the low-power mode; and wherein the repopulating is in response to the requesting the at least a portion of the cache to exit the low-power mode.
Claim 16
Dependent Claim
21 words
The method of claim 1 , further comprising flushing, in response to the requesting, a dirty one of the data entries.
Claim 17
Dependent Claim
21 words
The method of claim 1 , wherein the archiving comprises disabling modifications to the at least some of the tag entries.
Claim 18
Dependent Claim
53 words
The method of claim 16 , further comprising operating, after the disabling, the at least some of the tag entries in a power mode where at least a portion of each of the particular tags is retained in the at least some of the tag entries and is not accessible via the cache.
Claim 19
Dependent Claim
21 words
The method of claim 1 , wherein the archiving comprises copying at least a portion of each of the particular tags.
Claim 20
Dependent Claim
47 words
The method of claim 18 , further comprising after the copying, operating the at least some of the tag entries in a power mode where at least a portion of each of the particular tags is not retained in the at least some of the tag entries.
Claim 21
Dependent Claim
32 words
The method of claim 1 , further comprising accessing the cache as one or more of a first-level cache, a second-level cache, a third-level cache, an innermost cache, and an outermost cache.
Claim 22
Dependent Claim
166 words
A computer processing system comprising: a cache circuit comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; control logic enabled to direct archiving in a tag archive area, in response to receiving a request to enter a low-power mode, particular tags stored in at least some of the tag entries, additionally enabled, in response to the receiving the request, to direct reducing power provided to at least some of the data entries, enabled to direct repopulating a subset of the tag entries from the tag archive area, and the repopulating is subsequent to the reducing power; and wherein the cache circuit and the control logic are implemented within one or more integrated circuits.
Claim 23
Dependent Claim
166 words
A computer processing system comprising: a cache circuit comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; control logic enabled to direct archiving in a tag archive area, in response to receiving a request to enter a low-power mode, particular tags stored in at least some of the tag entries, additionally enabled, in response to the receiving the request, to direct reducing power provided to at least some of the data entries, enabled to direct repopulating a subset of the tag entries from the tag archive area, and the repopulating is subsequent to the reducing power; and wherein the cache circuit and the control logic are implemented within one or more integrated circuits.
Claim 24
Dependent Claim
17 words
The computer processing system of claim 21 , further comprising a processor coupled to the cache circuit.
Claim 25
Dependent Claim
21 words
The computer processing system of claim 22 , wherein the processor is enabled to access the cache circuit during the archiving.
Claim 26
Dependent Claim
21 words
The computer processing system of claim 22 , wherein the processor is enabled to access the cache circuit during the repopulating.
Claim 27
Dependent Claim
31 words
The computer processing system of claim 22 , wherein the control logic is additionally enabled to direct re-fetching into at least some of the data entries having corresponding repopulated tag entries.
Claim 28
Dependent Claim
17 words
The computer processing system of claim 25 , wherein the re-fetching is in accordance with cache coherency.
Claim 29
Dependent Claim
21 words
The computer processing system of claim 25 , wherein the processor is enabled to access the cache circuit during the re-fetching.
Claim 30
Dependent Claim
39 words
The computer processing system of claim 22 , wherein the processor is enabled to access the cache circuit as one or more of a first-level cache, a second-level cache, a third-level cache, an innermost cache, and an outermost cache.
Claim 31
Dependent Claim
23 words
The computer processing system of claim 21 , wherein the repopulating is in response to receiving a request to exit the low-power mode.
Claim 32
Dependent Claim
32 words
The computer processing system of claim 21 , wherein the control logic is additionally enabled to direct flushing a dirty one of the data entries in response to the receiving the request.
Claim 33
Dependent Claim
35 words
The computer processing system of claim 21 , wherein the control logic is additionally enabled to direct disabling modifications to the at least some of the tag entries in response to the receiving the request.
Claim 34
Dependent Claim
80 words
The computer processing system of claim 31 , wherein the control logic is additionally enabled to direct operating the at least some of the tag entries in a power mode subsequent to the disabling; and wherein at least a portion of each of the particular tags is retained in the at least some of the tag entries and is not accessible via the cache circuit while the at least some of the tag entries are operated in the power mode.
Claim 35
Dependent Claim
23 words
The computer processing system of claim 21 , wherein the archiving comprises copying at least a portion of each of the particular tags.
Claim 36
Dependent Claim
73 words
The computer processing system of claim 33 , wherein the control logic is additionally enabled to direct operating the at least some of the tag entries in a power mode subsequent to the copying; and wherein at least a portion of each of the particular tags is not retained in the at least some of the tag entries while the at least some of the tag entries are operated in the power mode.
Claim 37
Independent Claim
189 words
A medium readable by a computer system that contains descriptions that specify, when interpreted by the computer system, a representation of a circuit comprising: a cache of a processor, the cache comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; control logic enabled to operate with the cache; and wherein the control logic is additionally enabled in response to receiving a request to enter a low-power mode, to direct archiving in a tag archive area particular tags stored in at least some of the tag entries, is additionally enabled in response to the receiving the request, to direct reducing power provided to at least some of the data entries, is enabled to direct repopulating at least a subset of the tag entries from the tag archive area, and the repopulating is subsequent to the reducing power.
Claim 38
Independent Claim
189 words
A medium readable by a computer system that contains descriptions that specify, when interpreted by the computer system, a representation of a circuit comprising: a cache of a processor, the cache comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; control logic enabled to operate with the cache; and wherein the control logic is additionally enabled in response to receiving a request to enter a low-power mode, to direct archiving in a tag archive area particular tags stored in at least some of the tag entries, is additionally enabled in response to the receiving the request, to direct reducing power provided to at least some of the data entries, is enabled to direct repopulating at least a subset of the tag entries from the tag archive area, and the repopulating is subsequent to the reducing power.
Claim 39
Dependent Claim
20 words
The medium of claim 35 , wherein the cache is enabled to be accessed by the processor during the repopulating.
Claim 40
Dependent Claim
33 words
The medium of claim 35 , wherein the control logic is additionally enabled to direct re-fetching into at least some of the data entries having correspondence with the subset of the tag entries.
Claim 41
Dependent Claim
15 words
The medium of claim 37 , wherein the re-fetching is in accordance with cache coherency.
Claim 42
Dependent Claim
20 words
The medium of claim 37 , wherein the cache is enabled to be accessed by the processor during the re-fetching.
Claim 43
Dependent Claim
33 words
The medium of claim 35 , wherein the control logic is additionally enabled to direct disabling modifications to the at least some of the tag entries in response to the receiving the request.
Claim 44
Dependent Claim
76 words
The medium of claim 40 , wherein the control logic is enabled to direct operating the at least some of the tag entries in a power mode subsequent to the disabling; and wherein at least a portion of each of the particular tags is retained in the at least some of the tag entries and is not accessible via the cache while the at least some of the tag entries are operating in the power mode.
Claim 45
Dependent Claim
21 words
The medium of claim 35 , wherein the archiving comprises copying at least a portion of each of the particular tags.
Claim 46
Dependent Claim
71 words
The medium of claim 42 , wherein the control logic is additionally enabled to direct operating the at least some of the tag entries in a power mode subsequent to the copying; and wherein at least a portion of each of the particular tags is not retained in the at least some of the tag entries while the at least some of the tag entries are operating in the power mode.
Claim 47
Dependent Claim
38 words
The medium of claim 35 , wherein the cache is enabled to be accessed by the processor as one or more of a first-level cache, a second-level cache, a third-level cache, an innermost cache, and an outermost cache.
Claim 48
Independent Claim
156 words
A system comprising: means for caching, the means for caching comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; means for archiving particular tags stored in at least some of the tag entries, the means for archiving responsive to receiving a request to enter a low-power mode; means for reducing power provided to at least some of the data entries, the means for reducing power additionally responsive to the receiving the request; and means for repopulating at least a subset of the tag entries in accordance with the means for archiving, the means for repopulating operating subsequent to the means for reducing power.
Claim 49
Independent Claim
156 words
A system comprising: means for caching, the means for caching comprising a plurality of data entries and a plurality of tag entries, the tag entries in a one-to-one correspondence with the data entries, each of the data entries enabled to store a line of data, and each of the tag entries enabled to store a tag usable, at least in part, to identify any line of data in the corresponding data entry; means for archiving particular tags stored in at least some of the tag entries, the means for archiving responsive to receiving a request to enter a low-power mode; means for reducing power provided to at least some of the data entries, the means for reducing power additionally responsive to the receiving the request; and means for repopulating at least a subset of the tag entries in accordance with the means for archiving, the means for repopulating operating subsequent to the means for reducing power.
Claim 50
Dependent Claim
28 words
The system of claim 45 , further comprising means for re-fetching into at least some of the data entries having correspondence with the subset of the tag entries.
Claim 51
Dependent Claim
17 words
The system of claim 46 , wherein the means for re-fetching operates in accordance with cache coherency.
Claim 52
Dependent Claim
30 words
The system of claim 45 , further comprising means for flushing a dirty one of the data entries, the means for flushing operating in response to the receiving the request.
Claim 53
Dependent Claim
86 words
The system of claim 45 , wherein the means for reducing power is a first means for reducing power and further comprising second means for reducing power to the at least some of the tag entries, the second means for reducing power operating the at least some of the tag entries in a power mode where at least a portion of each of the particular tags is retained in the at least some of the tag entries and is not accessible via the means for caching.