Pseudo-differential analog front end circuit and image processing device

Claim 2

A pseudo-differential analog front end (AFE) circuit for receiving at least one analog image signal and generating at least one digital signal, wherein the pseudo-differential AFE circuit comprises at least one converting circuit and each converting circuit comprises: a first clamper for receiving the analog image signal and restoring a DC voltage level of the analog image signal to generate a first restored signal; a first input buffer for buffering the first restored signal and generating a buffered signal; and an analog-to-digital converter (ADC) having a positive input terminal and a negative input terminal, one of which receives the buffered signal and the other of which receives a comparing voltage, wherein the analog-to-digital converter converts a voltage difference between the two input terminals into the digital signal; wherein each of the analog-to-digital converters receives a common comparing voltage while the number of the at least one converting circuit is greater than one.

Claim 3

The pseudo-differential analog front end circuit according to claim 1 , which is disposed in a liquid crystal display controller and comprises three of the at least one converting circuit.

Claim 4

The pseudo-differential analog front end circuit according to claim 1 , which is disposed in a video decoder.

Claim 5

The pseudo-differential analog front end circuit according to claim 1 , wherein the first input buffer comprises: a variable current source having one terminal coupled to ground; and a NMOS transistor having its drain coupled to a power supply voltage, its source coupled to the other terminal of the variable current source and its gate receiving the first restored signal.

Claim 6

The pseudo-differential analog front end circuit according to claim 1 , wherein one of the at least one converting circuit further comprises: a second clamper for receiving a ground voltage corresponding to the analog image signal fed into the converting circuit and restoring a DC voltage level of the ground voltage to generate a second restored signal; and a second input buffer buffering the second restored signal and generating the comparing voltage.

Claim 7

The pseudo-differential analog front end circuit according to claim 5 , wherein the second input buffer comprises: a variable current source having one terminal coupled to ground; and a NMOS transistor having its drain coupled to a power supply voltage, its source coupled to the other terminal of the variable current source and its gate receiving the second restored signal.

Claim 8

The pseudo-differential analog front end circuit according to claim 1 , wherein one of the at least one converting circuit further comprises: a variable current source having one terminal coupled to a power supply voltage; and a resistor having one terminal coupled in series to the other terminal of the variable current source to form an input node, wherein the input node provides the comparing voltage and the other terminal of the resistor is coupled to a ground voltage corresponding to the analog image signal.

Claim 9

An image processing device for processing at least one analog image signal fed from a display card and generating at least one digital signal, comprising: a peripheral circuit having a ground terminal and electrically coupled with the display card for transmitting the at least one analog image signal; and a pseudo-differential analog front end circuit electrically coupled to the peripheral circuit and comprising at least one converting circuit, wherein each of the at least one converting circuit comprises: a first clamper for receiving the analog image signal and restoring a DC voltage level of the analog image signal to generate a first restored signal; a first input buffer for buffering the first restored signal and generating a buffered signal; and an analog-to-digital converter having a positive input terminal and a negative input terminal, one of which receives the buffered signal and the other of which receives a comparing voltage, wherein the analog-to-digital converter converts a voltage difference between the two input terminals into the digital signal; wherein each of the analog-to-digital converters receives a common comparing voltage while the number of the at least one converting circuit is greater than one.

Claim 10

An image processing device for processing at least one analog image signal fed from a display card and generating at least one digital signal, comprising: a peripheral circuit having a ground terminal and electrically coupled with the display card for transmitting the at least one analog image signal; and a pseudo-differential analog front end circuit electrically coupled to the peripheral circuit and comprising at least one converting circuit, wherein each of the at least one converting circuit comprises: a first clamper for receiving the analog image signal and restoring a DC voltage level of the analog image signal to generate a first restored signal; a first input buffer for buffering the first restored signal and generating a buffered signal; and an analog-to-digital converter having a positive input terminal and a negative input terminal, one of which receives the buffered signal and the other of which receives a comparing voltage, wherein the analog-to-digital converter converts a voltage difference between the two input terminals into the digital signal; wherein each of the analog-to-digital converters receives a common comparing voltage while the number of the at least one converting circuit is greater than one.

Claim 11

The image processing device according to claim 8 , which is disposed in a liquid crystal display controller and comprises three of the at least one converting circuit.

Claim 12

The image processing device according to claim 8 , which is disposed in a video decoder.

Claim 13

The image processing device according to claim 8 , wherein the first input buffer comprises: a variable current source having one terminal coupled to ground; and a NMOS transistor having its drain coupled to a power supply voltage, its source coupled to the other terminal of the variable current source and its gate receiving the first restored signal.

Claim 14

The image processing device according to claim 8 , wherein one of the at least one converting circuit further comprises: a second clamper coupled to the ground terminal of the peripheral circuit for generating a second restored signal; and a second input buffer for buffering the first restored signal and generating the comparing voltage.

Claim 15

The image processing device according to claim 12 , wherein the wherein the second input buffer comprises: a variable current source having one terminal coupled to ground; and a NMOS transistor having its drain coupled to a power supply voltage, its source coupled to the other terminal of the variable current source and its gate receiving the second restored signal.

Claim 16

The image processing device according to claim 8 , wherein one of the at least one converting circuit further comprises: a variable current source having its one terminal coupled to a power supply voltage; and a resistor having one terminal coupled in series to the other terminal of the variable current source to form an input node, wherein the input node provides the comparing voltage and the other terminal of the resistor is coupled to the ground terminal of the peripheral circuit.

Claim 17

The image processing device according to claim 8 , which is disposed on a printed circuit board.