Logic circuit and method thereof

Claim 2

A logic circuit, comprising: a random data generator for generating random data; a random mask device for generating random mask data based on received input data and the random data; and a logic device for executing a Boolean logic operation including the random mask data and outputting the results of the execution in a random mask type, the Boolean logic operation including a first Boolean logic operation not satisfying an associative law and a second Boolean logic operation satisfying an associative law.

Claim 3

The logic circuit of claim 1 , wherein the logic device includes a NOT operation device.

Claim 4

The logic circuit of claim 2 , wherein the NOT operation device includes: a NOT logic gate for receiving the random mask data; a first XOR logic gate for receiving first and second random data, the first and second random data being a portion of the generated random data; and a second XOR logic gate for receiving outputs of the NOT and first XOR logic gates.

Claim 5

The logic circuit of claim 3 , wherein the random mask data and the first and second random data each include n-bits, n being a natural number.

Claim 6

The logic circuit of claim 4 , wherein the NOT operation is executed based on corresponding bits of the random mask data and the first and second random data.

Claim 7

The logic circuit of claim 1 , wherein the logic device is an AND operation device.

Claim 8

The logic circuit of claim 1 , wherein the logic device includes a first at least one logic gate for executing a first Boolean logic operation satisfying the associative law and a second at least one logic gate for executing a second Boolean logic operation not satisfying the associative law.

Claim 9

The logic circuit of claim 6 , wherein the AND operation device includes: a first logic gate for receiving first and second random mask data to execute a first AND operation; a second logic gate for receiving the first random mask data and second random data to execute a second AND operation; a third logic gate for receiving the second random mask data and first random data to execute a third AND operation; a fourth logic gate for receiving the first and second random data to execute a fourth AND operation; a fifth logic gate for receiving outputs of the second and third logic gates to execute a first XOR operation; a sixth logic gate for receiving outputs of the fourth and fifth logic gates to execute a second XOR operation; a seventh logic gate for receiving an output of the sixth logic gate and third random data to execute a third XOR operation; and an eighth logic gate for receiving the first and seventh logic gates to execute a fourth XOR operation, the result of the fourth XOR operation being an output of the AND operation device, wherein the first, second and third random data are a portion of the generated random data.

Claim 10

The logic circuit of claim 8 , wherein the first random mask data is the result of a first input data and the first random data being executed with a fifth XOR operation and the second random mask data is the result of a second input data and the second random data being executed with a sixth XOR operation.

Claim 11

The logic circuit of claim 8 , wherein the random mask data and the first, second and third random data each include n-bits, n being a natural number.

Claim 12

The logic circuit of claim 10 , wherein the AND operation is executed based on corresponding bits of the random mask data and the first, second and third random data.

Claim 13

The logic circuit of claim 1 , wherein the logic device is an OR operation device.

Claim 14

The logic device of claim 12 , wherein the OR operation device includes: a first logic gate for receiving first and second random mask data to execute a first OR operation; a second logic gate for receiving the first random mask data and second random data to execute a first AND operation; a third logic gate for receiving the second random mask and first random data to execute a second AND operation; a fourth logic gate for receiving the first and second random data to execute a second OR operation; a fifth logic gate for receiving outputs of the second and third logic gates to execute a first XOR operation; a sixth logic gate for receiving outputs of the fourth and fifth logic gates to execute a second XOR operation; a seventh logic gate for receiving outputs of the sixth logic gate and third random data to execute a third XOR operation; and an eighth logic gate for receiving outputs of the first and seventh logic gates to execute a fourth XOR operation, the result of the fourth XOR operation being an output of the OR operation device, wherein the first, second and third random data are a portion of the generated random data.

Claim 15

The logic circuit of claim 13 , wherein the first random mask data is the result of a first input data and the first random data being executed with a fifth XOR operation and the second random mask data is the result of a second input data and the second random data being executed with a sixth XOR operation.

Claim 16

The logic circuit of claim 14 , wherein the random mask data and the first, second and third random data each include n-bits, n being a natural number.

Claim 17

The logic circuit of claim 15 , wherein the OR operation is executed based on corresponding bits of the random mask data and the first, second and third random data.

Claim 18

The logic circuit of claim 1 , wherein the logic device is a NAND operation device.

Claim 19

The logic circuit of claim 17 , wherein the NAND operation device includes an AND operation device and a NOT operation device.

Claim 20

The logic circuit of claim 1 , wherein the logic device is a NOR operation device.

Claim 21

The logic circuit of claim 16 , wherein the NOR operation device includes an OR operation device and a NOT operation device.

Claim 24

The method of claim 21 , wherein the at least one Boolean logic operation includes a first NOT operation.

Claim 25

The method of claim 22 , wherein the first NOT operation includes: executing a second NOT operation on the random mask data; executing a first XOR operation on received first and second random data, the first and second random data being a portion of the generated random data; and executing a second XOR operation on the outputs of the NOT operation and the first XOR operation.

Claim 26

The method of claim 21 , wherein the at least one Boolean logic operation includes a first AND operation.

Claim 27

The method of claim 24 , wherein the first AND operation includes: receiving first and second random mask data to execute a second AND operation, the first and second random mask data being a portion of the generated random mask data; receiving the first random mask data and second random data to execute a third AND operation; receiving the second random mask data and first random data to execute a fourth AND operation; receiving the first and second random data to execute a fifth AND operation; receiving outputs of the second and third logic gates to execute a first XOR operation; receiving outputs of the fourth and fifth logic gates to execute a second XOR operation; receiving an output of the sixth logic gate and third random data to execute a third XOR operation; and receiving outputs of the first and seventh logic gates to execute a fourth XOR operation, the output of the fourth XOR operation being the result of the first AND operation, wherein the first, second and third random data are a portion of the generated random data.

Claim 28

The method of claim 25 , wherein the first and second random mask data and the first, second and third random data each include n-bits, n being a natural number.

Claim 29

The method of claim 26 , wherein the first AND operation is executed based on corresponding bits of the first and second random mask data and the first, second and third random data.

Claim 30

The method of claim 21 , wherein the at least one Boolean logic operation includes a first OR operation.

Claim 31

The method of claim 28 , wherein the first OR operation includes: receiving first and second random mask data to execute a second OR operation; receiving the first random mask data and second random data to execute a first AND operation; receiving the second random mask data and first random data to execute a second AND operation; receiving the first and second random data to execute a third OR operation; receiving outputs of the second and third logic gates to execute a first XOR operation; receiving outputs of the third and fourth logic gates to execute a second XOR operation; receiving an output of the sixth logic gate and third random data to execute a third XOR operation; and receiving outputs of the first and seventh logic gates to execute a fourth XOR operation, the output of the fourth XOR operation being the result of the first OR operation, wherein the first, second and third random data are a portion of the generated random data.

Claim 32

The method of claim 29 , wherein the first and second random mask data and the first, second and third random data each include n-bits, n being a natural number.

Claim 33

The method of claim 28 , wherein the first OR operation is executed based on corresponding bits of the first and second random mask data and the first, second and third random data.

Claim 34

The method of claim 21 , wherein the at least one Boolean logic operation includes a NAND operation.

Claim 35

The method of claim 32 , wherein the NAND operation includes an AND operation and a NOT operation.

Claim 36

The method of claim 21 , wherein the at least one Boolean logic operation includes a NOR operation.

Claim 37

The method of claim 34 , wherein the NOR operation includes an OR operation and a NOT operation.