US7268049B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Structure and method for manufacturing MOSFET with super-steep retrograded island
Assignee: GlobalFoundries Inc
•
Filing: 2004-09-30
•
Granted: 2007-09-11
•
Expires: 2024-09-30
Abstract
Abstract The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si 1-x-y Ge x Z y , where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
Inventors
- 👤 Huilong Zhu
- 👤 Effendi Leobandung
- 👤 Anda C. Mocuta
- 👤 Dan M. Mocuta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/791; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/601; H10D30/797; H10D62/00; H10D62/01; H10D62/021; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/314; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10P; H10P30/00; H10P30/20; H10P30/222; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
186 words
A method of forming a semiconducting device comprising: providing a layered structure comprising a substrate, a low diffusivity layer of a first conductivity type dopant atop said substrate, and a channel layer atop said low diffusivity layer of said first conductivity type dopant, wherein said low diffusivity layer of said first conductivity type dopant comprises Si 1-x-y Ge y , in which Z is a diffusion inhibiting dopant selected from the group consisting of carbon, xenon, krypton. argon, nitrogen, and combinations thereof; forming a gate region atop a protected surface of said channel layer of said layered structure; etching said layered structure selective to said gate region to expose a surface of said substrate, where a remaining portion of said low diffusivity layer of said first conductivity type dopant provides a retrograded island substantially aligned with said gate stack having a first dopant concentration to reduce short-channel effects without increasing device leakage; growing a Si-containing material atop said recessed surface of said substrate; forming offset spacers abutting said gate region; and doping said Si-containing material with a second conductivity type dopant at a second dopant concentration.
Claim 2
Independent Claim
186 words
A method of forming a semiconducting device comprising: providing a layered structure comprising a substrate, a low diffusivity layer of a first conductivity type dopant atop said substrate, and a channel layer atop said low diffusivity layer of said first conductivity type dopant, wherein said low diffusivity layer of said first conductivity type dopant comprises Si 1-x-y Ge y , in which Z is a diffusion inhibiting dopant selected from the group consisting of carbon, xenon, krypton. argon, nitrogen, and combinations thereof; forming a gate region atop a protected surface of said channel layer of said layered structure; etching said layered structure selective to said gate region to expose a surface of said substrate, where a remaining portion of said low diffusivity layer of said first conductivity type dopant provides a retrograded island substantially aligned with said gate stack having a first dopant concentration to reduce short-channel effects without increasing device leakage; growing a Si-containing material atop said recessed surface of said substrate; forming offset spacers abutting said gate region; and doping said Si-containing material with a second conductivity type dopant at a second dopant concentration.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein said first conductivity type dopant is an n-type dopant and said second conductivity type dopant is a p-type dopant.
Claim 4
Dependent Claim
25 words
The method of claim 1 wherein said first conductivity type dopant is a p-type dopant and said second conductivity type dopant is an n-type dopant.
Claim 5
Dependent Claim
81 words
The method of claim 1 wherein said low diffusivity layer of said first conductivity type dopant is formed by epitaxially growing SiGe to a thickness ranging from about 10 nm to about 50 nm atop said substrate; doping said diffusion inhibiting dopant at a concentration ranging from about 1×10 18 atoms/cm 3 to about 1×10 20 atoms/cm 3 ; and doping said first conductivity dopant at a concentration ranging from about 5×10 18 atoms/cm 3 to 1×10 20 atoms/cm 3 .
Claim 6
Dependent Claim
17 words
The method of claim 1 wherein said second dopant concentration is greater than said first dopant concentration.
Claim 7
Dependent Claim
34 words
The method of claim 2 wherein said growing said Si-containing material atop said exposed surface of said substrate comprises epitaxially growing SiGe, wherein said Si-containing material transfers a compressive stress to said channel layer.
Claim 8
Dependent Claim
34 words
The method of claim 3 wherein said growing said Si-containing material atop said exposed surface of said substrate comprises epitaxially growing Si:C, wherein said Si-containing material transfers a tensile stress to said channel layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-09-10 | 2011-03-12 | 2011-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-09-10 | 2015-03-12 | 2015-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-09-10 | 2019-03-12 | 2019-09-11 | $7700.00 | Window Closed / Lapsed |