Duty cycle correcting circuits having a variable gain and methods of operating the same

Claim 2

A duty cycle correcting circuit, comprising: a frequency detecting means for detecting a frequency of an input clock signal to generate a control signal; a duty cycle detecting means for detecting a duty cycle of an output clock signal to generate first and second duty cycle detecting signals; and a duty cycle correcting means for adjusting a gain in response to the control signal and generating a corrected clock signal in response to the first and second duty cycle detecting signals, wherein the input signal comprises an input clock signal and the output signal comprises the corrected clock signal, wherein the duty cycle correcting means comprises: a gain adjusting circuit that adjusts the gain of the duty cycle correcting means; and an output circuit that outputs the corrected output signal based on the input signal and the adjusted gain.

Claim 3

The duty cycle correcting circuit of claim 1 wherein the control signal comprises a predetermined number of signals.

Claim 4

The duty cycle correcting circuit of claim 2 wherein the duty cycle correcting means reduces the gain responsive to the control signal when a frequency of the input clock signal is increased.

Claim 5

The duty cycle correcting circuit of claim 3 wherein the output circuit includes: a main amplifying portion that amplifies a voltage difference between the input clock signal and an inverted input clock signal; and the gain adjusting circuit includes: a sub amplifying portion that adjusts a gain responsive to the control signal and amplifies a voltage difference between the first and second duty cycle detecting signal; and wherein a common output signal of the main and sub amplifying portion is generated as the corrected clock signal.

Claim 6

The duty cycle correcting circuit of claim 2 wherein the frequency detecting means includes: a pulse generating circuit that detects a frequency of the input clock signal and generates a detecting signal based on the detected frequency of the input clock signal; a latch circuit that latches the detecting signal from the pulse generating portion to provide a frequency detecting signal; and a control signal generating circuit that generates the control signals responsive to the frequency detecting signal.

Claim 7

The duty cycle correcting circuit of claim 5 wherein the control signal generating circuit sets at least one of the control signals to a logic “high” level responsive to the frequency detecting signal from the latch circuit.

Claim 8

The duty cycle correcting circuit of claim 5 wherein the control signal generating circuit includes: a signal confirming portion that generates at least one frequency confirming signal maintained at a logic “high” level responsive to a selected at least one of the frequency detecting signals having a logic “high” level and another of the frequency detecting signals having a logic “low” level; and a signal detecting portion that sets a state of an upper frequency or a lower frequency one of the frequency confirming signals to a logic “high” level to generate the control signals when the at least one frequency confirming signal from the signal confirming portion is set to a logic “high” level.

Claim 9

The duty cycle correcting circuit of claim 5 wherein the pulse generating circuit includes: a pulse generator that delays the input clock signal by a predetermined time period and generates a pulse signal responsive to an edge of the delayed input clock signal; and a gate circuit that generates the detecting signal based on the input clock signal and the pulse signal.

Claim 10

The duty cycle correcting circuit of claim 8 wherein the detecting signal comprises a plurality of detecting signals, the frequency detecting signal comprises a plurality of frequency detecting signals and wherein the control signal generating circuit sets at least one of the control signals responsive to an edge of a frequency detecting signal.

Claim 11

A duty cycle correcting circuit, comprising: a frequency detecting means for detecting a frequency of an input clock signal to generate a control signal; a duty cycle detecting means for detecting a duty cycle of an output clock signal to generate first and second duty cycle detecting signals; and a duty cycle correcting means for adjusting a first delay time in response to the control signal and the first duty cycle detecting signal and detecting an edge of the input clock signal to generate a first pulse signal and for adjusting a second delay time in response to the control signal and the second duty cycle detecting signal and detecting an edge of the input clock signal to generate a second pulse signal and latching the first and the second pulse signals to generate the corrected clock signal, wherein the input signal comprises an input clock signal and the output signal comprises the corrected clock signal.

Claim 12

A duty cycle correcting circuit, comprising: a frequency detecting means for detecting a frequency of an input clock signal to generate a control signal; a duty cycle detecting means for detecting a duty cycle of an output clock signal to generate first and second duty cycle detecting signals; and a duty cycle correcting means for adjusting a first delay time in response to the control signal and the first duty cycle detecting signal and detecting an edge of the input clock signal to generate a first pulse signal and for adjusting a second delay time in response to the control signal and the second duty cycle detecting signal and detecting an edge of the input clock signal to generate a second pulse signal and latching the first and the second pulse signals to generate the corrected clock signal, wherein the input signal comprises an input clock signal and the output signal comprises the corrected clock signal.

Claim 13

The duty cycle correcting circuit of claim 10 wherein the duty cycle correcting means includes: a first pulse signal generating portion that adjusts the first delay time responsive to the control signal and the first duty cycle detecting signal and detects an edge of the input clock signal to generate a first pulse signal; a second pulse signal generating portion that adjusts the second delay time responsive to the control signal and the second duty cycle detecting signal and detects an edge of the input clock signal to generate a second pulse signal; and a latch portion that combines the first pulse signal and the corrected clock signal to generate an inverted corrected clock signal and combines the second pulse signal and the inverted corrected clock signal to generate the corrected clock signal.

Claim 14

The duty cycle correcting circuit of claim 10 wherein the frequency detecting means includes: a pulse generating circuit that detects a frequency of the input clock signal and generates a detecting signal based on the detected frequency of the input clock signal; a latch circuit that latches the detecting signal from the pulse generating portion to provide a frequency detecting signal; and a control signal generating circuit that generates the control signals responsive to the frequency detecting signal.

Claim 15

The duty cycle correcting circuit of claim 12 wherein the frequency detecting circuit is configured to detect at least a high frequency and a low frequency and wherein the frequency detecting circuit includes a control signal generating circuit that sets a greater number of the control signals to the active state when a low frequency is detected than when a high frequency is detected.

Claim 16

The duty cycle correcting circuit of claim 12 wherein the control signals comprise at least three control signals and wherein the frequency detecting circuit is further configured to detect an intermediate frequency having a frequency between the high frequency and the low frequency and wherein the control signal generating circuit is configured to set a greater number of the control signals to the active state when an intermediate frequency is detected than when a high frequency is detected and a lesser number of the control signals to the active state when an intermediate frequency is detected than when a low frequency is detected and wherein the active state comprises a logic “high” level.

Claim 17

A duty cycle correcting method, comprising: detecting a frequency of an input signal to generate a corresponding frequency detecting signal generating control signals in response to the corresponding frequency detecting signal; generating first and second duty detecting signals by detecting a duty cycle of an output signal; amplifying a voltage difference between the input signal and an inverted input clock signal which has an inverted phase of the input signal; adjusting a gain of a duty cycle correcting circuit in response to the control signals; and amplifying a voltage difference between first and second duty cycle detecting signals to generating a corrected clock signal, wherein the input signal comprises an input clock signal and wherein the output signal comprises the corrected clock signal.

Claim 18

A duty cycle correcting method, comprising: detecting a frequency of an input signal to generate a corresponding frequency detecting signal generating control signals in response to the corresponding frequency detecting signal; generating first and second duty detecting signals by detecting a duty cycle of an output signal; amplifying a voltage difference between the input signal and an inverted input clock signal which has an inverted phase of the input signal; adjusting a gain of a duty cycle correcting circuit in response to the control signals; and amplifying a voltage difference between first and second duty cycle detecting signals to generating a corrected clock signal, wherein the input signal comprises an input clock signal and wherein the output signal comprises the corrected clock signal.

Claim 19

The method of claim 15 wherein correcting a duty cycle includes reducing the gain responsive to the control signal when a frequency of the input clock signal is increased.

Claim 20

The method of claim 16 wherein correcting a duty cycle includes: amplifying a voltage difference between the input clock signal and an inverted input clock signal to provide an output to a common output signal line; and wherein adjusting a gain comprises adjusting a gain responsive to the control signal and amplifying a voltage difference between the first and second duty cycle detecting signal to provide an output to the common output signal line, wherein the common output signal line is the corrected clock signal.

Claim 21

The method of claim 15 wherein generating control signals comprises generating control signals such that a state of upper and/or lower frequency detecting signals of the corresponding frequency detecting signal is changed to generate the control signal when a state of the corresponding frequency detecting signal is changed.

Claim 22

The method of claim 18 wherein generating control signals includes maintaining the corresponding frequency detecting signal at a logic “high” level to provide a corresponding frequency confirming signal when the corresponding frequency detecting signal has a logic “high” level, and an upper and/or lower frequency detecting signal of the corresponding frequency detecting signal has a logic “low” level; and changing a state of an upper and/or lower corresponding frequency confirming signal of the corresponding frequency confirming signal to a logic “high” level to generate the control signals when the corresponding frequency confirming signal is changed to a logic “high” level.

Claim 23

The method of claim 15 wherein the control signals comprise a predetermined number of signals.

Claim 24

The method of claim 20 wherein the detecting a frequency includes detecting a frequency of the input clock signal to generate a detecting signal corresponding to the frequency of the input clock signal; latching a detecting signal to generate a corresponding frequency detecting signal; and generating the control signals responsive to the corresponding frequency detecting signal.

Claim 25

The method of claim 21 wherein detecting a frequency of the input clock signal to generate a detecting signal includes: delaying the input clock signal by a predetermined time period and detecting an edge of the input clock signal to generate a corresponding pulse signal; and combining the input clock signal and the corresponding pulse signal to generate the corresponding detecting signal.

Claim 26

A duty cycle correcting method, comprising: detecting a frequency of an input signal to generate a corresponding frequency detecting signal; generating control signals in response to the corresponding frequency detecting signal; generating first and second duty cycle detecting signals by detecting a duty cycle of an output clock signal; adjusting a delay time in response to the control signals and the first duty cycle detecting signal and detecting an edge of the input clock signal to generate a first pulse signal; adjusting a delay time in response to the control signals and the second duty detecting signal and detecting an edge of an inverted input clock signal which has an inverted phase of the input clock signal to generate a first pulse signal; and latching the first and the second pulse signals to generate a corrected clock signal, wherein the input signal comprises an input clock signal and wherein the output signal comprises the corrected clock signal.

Claim 27

A duty cycle correcting method, comprising: detecting a frequency of an input signal to generate a corresponding frequency detecting signal; generating control signals in response to the corresponding frequency detecting signal; generating first and second duty cycle detecting signals by detecting a duty cycle of an output clock signal; adjusting a delay time in response to the control signals and the first duty cycle detecting signal and detecting an edge of the input clock signal to generate a first pulse signal; adjusting a delay time in response to the control signals and the second duty detecting signal and detecting an edge of an inverted input clock signal which has an inverted phase of the input clock signal to generate a first pulse signal; and latching the first and the second pulse signals to generate a corrected clock signal, wherein the input signal comprises an input clock signal and wherein the output signal comprises the corrected clock signal.

Claim 28

The method of claim 23 wherein detecting a frequency comprises detecting at least a high frequency and a low frequency and wherein detecting a frequency further comprises setting a greater number of the control signals to the active state when a low frequency is detected than when a high frequency is detected.

Claim 29

The method of claim 24 wherein the control signals comprise at least three control signals and wherein detecting a frequency further comprises detecting an intermediate frequency having a frequency between the high frequency and the low frequency and wherein detecting a frequency further comprises setting a greater number of the control signals to the active state when an intermediate frequency is detected than when a high frequency is detected and a lesser number of the control signals to the active state when an intermediate frequency is detected than when a low frequency is detected.