US6979996B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for automatic elimination of round-trip delay errors induced by automatic test equipment calibration
Assignee: International Business Machines Corp
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Filing: 2003-09-15
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Granted: 2005-12-27
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Expires: 2023-09-15
Abstract
Abstract A Dual Channel Mode for selecting specific waveform sets or characters in the applied data eliminates round trip delay errors in automatic test equipment. Drive waveforms and data are directed by a compiler to a first channel, while receive waveforms and data are directed to a second channel, eliminating false readings induced by the round-trip delays. The drive and compare waveforms are separated onto the first and second channels of electronics.
Inventors
- 👤 Thomas J. Fleishman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31928; G01R31/3193; G01R31/31937
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
217 words
An apparatus for eliminating time delay errors during automatic testing of electronics, using automatic test equipment comprising: device interface board wiring having a device interface board signal time delay; a device socket connected to said device interface board wiring, having a device socket signal time delay; first channel and second channel pin electronics wiring connected to said device interface board wiring, having pin electronics signal time delays; a first channel including a set of driver electronics, said set of driver electronics including inputs for receiving drive data, drive timing edge source data, and a first channel output, said first channel output transmitting information to a device under test through said first channel pin electronics, said device interface board wiring, and said device socket; a second channel having a set of receiver electronics, said set of receiver electronics including inputs for comparison data source information, comparison timing edge source information, and an output from said device under test; and a compiler to automatically route said drive timing edge source data, signal levels, and data to said first channel, and said comparison timing edge source information, signal levels, and data to said second channel; said first and second channels separate and distinct from one another and compensating for time delay errors when said device under test is electronically exercised.
Claim 2
Independent Claim
217 words
An apparatus for eliminating time delay errors during automatic testing of electronics, using automatic test equipment comprising: device interface board wiring having a device interface board signal time delay; a device socket connected to said device interface board wiring, having a device socket signal time delay; first channel and second channel pin electronics wiring connected to said device interface board wiring, having pin electronics signal time delays; a first channel including a set of driver electronics, said set of driver electronics including inputs for receiving drive data, drive timing edge source data, and a first channel output, said first channel output transmitting information to a device under test through said first channel pin electronics, said device interface board wiring, and said device socket; a second channel having a set of receiver electronics, said set of receiver electronics including inputs for comparison data source information, comparison timing edge source information, and an output from said device under test; and a compiler to automatically route said drive timing edge source data, signal levels, and data to said first channel, and said comparison timing edge source information, signal levels, and data to said second channel; said first and second channels separate and distinct from one another and compensating for time delay errors when said device under test is electronically exercised.
Claim 3
Dependent Claim
35 words
The apparatus of claim 1 wherein said time delay errors comprise round-trip timing errors from said automatic test equipment to said device under test, and from said device under test to said automatic test equipment.
Claim 4
Dependent Claim
33 words
The apparatus of claim 2 wherein said time delay errors comprise a summation of said pin electronics signal time delays, said device interface board signal time delay, and said device socket time delay.
Claim 5
Dependent Claim
20 words
The apparatus of claim 1 wherein said first channel and second channel pin electronics signal time delays are approximately equal.
Claim 6
Dependent Claim
14 words
The apparatus of claim 1 wherein said set of receiver electronics includes a comparator.
Claim 7
Dependent Claim
37 words
The apparatus of claim 1 wherein at least one of said second channel inputs is electrically connected to said first channel output through said first and second channel pin electronics wiring and said device interface board wiring.
Claim 8
Dependent Claim
26 words
The apparatus of claim 1 further including a set of receiver electronics in said first channel and a set of driver electronics in said second channel.
Claim 9
Independent Claim
69 words
A method for eliminating time delay errors during automatic testing of a device under test comprising: separating drive and compare waveforms onto first and second channels of electronics; routing drive timing edge source data, signal levels, and data to said first channel; routing comparison timing edge source information, signal levels, and data to said second channel; and compensating for said time delay errors when testing said device under test.
Claim 10
Independent Claim
69 words
A method for eliminating time delay errors during automatic testing of a device under test comprising: separating drive and compare waveforms onto first and second channels of electronics; routing drive timing edge source data, signal levels, and data to said first channel; routing comparison timing edge source information, signal levels, and data to said second channel; and compensating for said time delay errors when testing said device under test.
Claim 11
Dependent Claim
44 words
The method of claim 8 wherein said routing further includes programming an automatic test equipment compiler to configure internal signal switches to force all drive edges and waveforms to occur on said first channel and all compare waveforms to occur on said second channel.
Claim 12
Dependent Claim
31 words
The method of claim 9 further comprising applying said drive edge waveforms and said compare waveforms in a vector file identifying an appropriate tester cycle type and drive or compare data.
Claim 13
Dependent Claim
22 words
The method of claim 8 further including self-calibrating automatic test equipment for all pins, and nulling out any delays due to wiring.
Claim 14
Dependent Claim
27 words
The method of claim 9 further including eliminating overlap of edges and data induced by implementing auto-correction schemes of said automatic test equipment's self-calibration using TDR delays.
Claim 15
Dependent Claim
92 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for negating time delay errors during automatic testing of a device under test, said method steps comprising: separating drive and compare waveforms onto first and second channels of electronics; routing drive timing edge source data, signal levels, and data to said first channel; routing comparison timing edge source information, signal levels, and data to said second channel; and compensating for said time delay errors when testing said device under test.
Claim 16
Dependent Claim
92 words
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for negating time delay errors during automatic testing of a device under test, said method steps comprising: separating drive and compare waveforms onto first and second channels of electronics; routing drive timing edge source data, signal levels, and data to said first channel; routing comparison timing edge source information, signal levels, and data to said second channel; and compensating for said time delay errors when testing said device under test.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-12-26 | 2009-06-27 | 2009-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-12-26 | 2013-06-27 | 2013-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-12-26 | 2017-06-27 | 2017-12-27 | $7700.00 | Window Closed / Lapsed |