US6954095B2
Expired / Lapsed
US
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Apparatus and method for generating clock signals
Assignee: Rambus Inc
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Filing: 2004-03-22
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Granted: 2005-10-11
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Expires: 2024-03-22
Abstract
Abstract A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.
Inventors
- 👤 Benedict C. Lau
- 👤 Stefanos Sidiropoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:31
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
117 words
A system, comprising: a random access memory device; a first signal line coupled to the random access memory device, the first signal line to carry a first signal; a second signal line coupled to the random access memory device, the second signal line to carry a second signal; and a memory controller coupled to the first signal line and the second signal line, wherein the memory controller includes a delay locked loop to generate the first signal, wherein the first signal is used to transmit data to the random access memory device, the delay locked loop to receive the second signal such that the second signal is used to sample read data provided by the memory device.
Claim 2
Independent Claim
117 words
A system, comprising: a random access memory device; a first signal line coupled to the random access memory device, the first signal line to carry a first signal; a second signal line coupled to the random access memory device, the second signal line to carry a second signal; and a memory controller coupled to the first signal line and the second signal line, wherein the memory controller includes a delay locked loop to generate the first signal, wherein the first signal is used to transmit data to the random access memory device, the delay locked loop to receive the second signal such that the second signal is used to sample read data provided by the memory device.
Claim 3
Dependent Claim
34 words
The system as recited in claim 1 , wherein the memory controller includes a driver such that the first signal is used to transmit data to the memory device by way of the driver.
Claim 4
Independent Claim
23 words
The system as recited in 1 , wherein the memory controller includes a sampler to sample the read data using the second signal.
Claim 5
Independent Claim
23 words
The system as recited in 1 , wherein the memory controller includes a sampler to sample the read data using the second signal.
Claim 6
Dependent Claim
42 words
The system as recited in claim 4 , further comprising: a first delay element coupled in a feedback path of the delay-locked loop to change a phase difference between the second signal and a reference clock signal by a first time period.
Claim 7
Dependent Claim
43 words
The system as recited in claim 4 , further comprising: a second delay element outside the feedback path of the delay-locked loop to receive the second signal, and to delay the first signal relative to the second signal by the first time period.
Claim 8
Dependent Claim
29 words
The system of claim 1 , further including a clock generator to generate the second signal, wherein the second signal propagates from the clock generator to the memory controller.
Claim 9
Dependent Claim
19 words
The system of claim 6 , wherein the second signal is terminated after being received by the memory controller.
Claim 10
Dependent Claim
22 words
The system of claim 1 , wherein the first signal is a clock signal and the second signal is a clock signal.
Claim 11
Dependent Claim
30 words
The system as recited in claim 1 , wherein the delay-locked loop further includes a phase detector to identify phase differences between the second signal and the reference clock signal.
Claim 12
Dependent Claim
17 words
The system as recited in claim 9 , wherein the phase detector is a zero phase detector.
Claim 13
Dependent Claim
28 words
The system as recited in claim 9 , wherein the phase detector is an integration sampler to integrate the first signal with respect to the reference clock signal.
Claim 14
Dependent Claim
28 words
The system as recited in claim 1 , wherein the delay-locked loop further includes a 180 degree phase shift circuit to adjust a phase of the second signal.
Claim 15
Dependent Claim
28 words
The system as recited in claim 12 , wherein the 180 degree phase shift is accomplished by switching over the first signal line and the second signal line.
Claim 16
Dependent Claim
42 words
The system as recited in claim 1 , wherein first data of the read data is sampled on a rising edge of the second signal and second data of the read data is sampled on a falling edge of the second signal.
Claim 17
Dependent Claim
37 words
The system as recited in claim 1 , wherein the delay lock loop generates a receive clock using the second signal, wherein the receive clock is used to sample read data by way of the second signal.
Claim 18
Dependent Claim
32 words
The system of claim 15 , wherein the delay locked loop generates the receive clock such that a phase of the receive clock is aligned with a phase of the second signal.
Claim 19
Independent Claim
100 words
A method of operation in a memory controller comprising: generating a first signal using a single delay-locked loop wherein the first signal is used to time data transmission; changing a phase difference between the first signal and a reference signal by a first time period using a second delay element outside the feedback path of the delay-locked loop circuit; and receiving a second signal to be delayed relative to the first signal by the first time period using a first delay element in a feedback path of the delay-locked loop, wherein the second signal is used to time data reception.
Claim 20
Independent Claim
100 words
A method of operation in a memory controller comprising: generating a first signal using a single delay-locked loop wherein the first signal is used to time data transmission; changing a phase difference between the first signal and a reference signal by a first time period using a second delay element outside the feedback path of the delay-locked loop circuit; and receiving a second signal to be delayed relative to the first signal by the first time period using a first delay element in a feedback path of the delay-locked loop, wherein the second signal is used to time data reception.
Claim 21
Dependent Claim
17 words
The method as recited in claim 17 , further comprising transmitting data by way of a driver.
Claim 22
Independent Claim
17 words
The method as recited in 17 , further comprising sampling the read data using the second signal.
Claim 23
Independent Claim
17 words
The method as recited in 17 , further comprising sampling the read data using the second signal.
Claim 24
Dependent Claim
28 words
The method as recited in claim 17 , further comprising changing a phase difference between the second signal and a reference clock signal by a first time period.
Claim 25
Dependent Claim
24 words
The method as recited in claim 20 , further comprising delaying the first signal relative to the second signal by the first time period.
Claim 26
Dependent Claim
25 words
The method of claim 17 , further comprising generating the second signal from a clock generator and propagating the second signal to a memory controller.
Claim 27
Dependent Claim
22 words
The method of claim 22 , further comprising terminating the second signal after the second signal is received by the memory controller.
Claim 28
Dependent Claim
22 words
The method of claim 17 , wherein the first signal is a clock signal and the second signal is a clock signal.
Claim 29
Dependent Claim
22 words
The method as recited in claim 17 , further comprising identifying phase differences between the second signal and the reference clock signal.
Claim 30
Dependent Claim
15 words
The method as recited in claim 25 , further comprising detecting a zero phase difference.
Claim 31
Dependent Claim
21 words
The method as recited in claim 25 , further comprising integrating the first signal with respect to the reference clock signal.
Claim 32
Dependent Claim
20 words
The method as recited in claim 17 , further comprising adjusting a phase of the second signal by 180 degrees.
Claim 33
Dependent Claim
28 words
The method as recited in claim 28 , further comprising switching over the first signal line and the second signal line to effect the 180 degree phase shift.
Claim 34
Dependent Claim
42 words
The method as recited in claim 17 , wherein first data of the read data is sampled on a rising edge of the second signal and second data of the read data is sampled on a falling edge of the second signal.
Claim 35
Dependent Claim
34 words
The method as recited in claim 17 , further comprising generating a receive clock using the second signal, wherein the receive clock is used to sample read data by way of the second signal.
Claim 36
Dependent Claim
29 words
The method of claim 31 , further comprising generating the receive clock such that a phase of the receive clock is aligned with a phase of the second signal.
Claim 37
Independent Claim
113 words
A system, comprising: an electronic data store; a controller for the electronic data store, including: a delay-locked loop to receive a second signal, wherein the delay-locked loop includes: a first delay element coupled in a feedback path of the delay-locked loop, wherein the first delay element changes a phase difference between the second signal and a reference clock signal by a first time period, and a second delay element outside the feedback path to receive the second signal and output a first signal that is delayed relative to the second signal by the first time period, and a phase detector to determine phase differences between the second signal and the reference clock signal.
Claim 38
Independent Claim
113 words
A system, comprising: an electronic data store; a controller for the electronic data store, including: a delay-locked loop to receive a second signal, wherein the delay-locked loop includes: a first delay element coupled in a feedback path of the delay-locked loop, wherein the first delay element changes a phase difference between the second signal and a reference clock signal by a first time period, and a second delay element outside the feedback path to receive the second signal and output a first signal that is delayed relative to the second signal by the first time period, and a phase detector to determine phase differences between the second signal and the reference clock signal.
Claim 39
Dependent Claim
17 words
The system as recited in claim 33 , wherein the phase detector comprises a zero phase detector.
Claim 40
Dependent Claim
19 words
The system as recited in claim 33 , wherein the delay-locked loop further includes a 180 degrees phase shifter.
Claim 41
Dependent Claim
25 words
The system as recited in claim 33 , wherein the first and second signals provide timing for address multiplexing operations of the electronic data store.
Claim 42
Dependent Claim
25 words
The system as recited in claim 33 , further comprising an integration sampler to integrate the first signal with respect to the reference clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-10-10 | 2009-04-11 | 2009-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-10-10 | 2013-04-11 | 2013-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-10-10 | 2017-04-11 | 2017-10-11 | $7700.00 | Window Closed / Lapsed |