US6943602B1
Expired / Lapsed
US
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Delay locked loop and locking method thereof
Assignee: Mosaid Technologies Inc
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Filing: 2004-12-30
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Granted: 2005-09-13
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Expires: 2024-12-30
Abstract
Abstract The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparator for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing unit for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
Inventors
- 👤 Hyun-woo Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:33
CPC Classifications
G; G11; G11C; G11C8/00; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/089
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
108 words
A delay locked loop with at least one delay line, comprising: a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
Claim 2
Dependent Claim
108 words
A delay locked loop with at least one delay line, comprising: a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
Claim 3
Dependent Claim
41 words
The delay locked loop as recited in claim 1 , wherein the multiplexing means selects the second clock in case that the control signal to decrease the delay amount is inputted thereto when the first clock lags behind the feedback clock.
Claim 4
Dependent Claim
41 words
The delay locked loop as recited in claim 1 , wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
Claim 5
Dependent Claim
36 words
The delay locked loop as recited in claim 1 , wherein the output of the shift register which is inputted into the multiplexing means is a maximum shift bit signal or a minimum shift bit signal.
Claim 6
Dependent Claim
68 words
The delay locked loop as recited in claim 1 , wherein the phase comparing means outputs the control signal to increase the delay amount when the first signal is in logic low level at a rising edge of the feedback clock, and outputs the control signal to decrease the delay amount when the first signal is in logic high level at a rising edge of the feedback clock.
Claim 7
Dependent Claim
66 words
The delay locked loop as recited in claim 4 , wherein the multiplexing means includes: a multiplexer selector for outputting a selection signal to select one between the first and the second clocks by using the output of the phase comparator and the output of the shift register; and a multiplexer for outputting the selected one between the first and the second clocks of the buffer.
Claim 8
Dependent Claim
133 words
The delay locked loop as recited in claim 6 , wherein the multiplexer selector includes: a first NAND gate for performing a logic NAND operation to the minimum shift bit signal and the command to decrease the delay amount; a second NAND gate for performing a logic NAND operation to the maximum shift bit signal and the command to increase the delay amount; a NOR gate for performing a logic NOR operation to the outputs of the first and the second NAND gates; a majority voter for outputting a predetermined signal when the output of the NOR gate is maintained for a predetermined time; a switch which is switched by the output of the majority voter and is reset by a reset signal; and a latch for latching the output of the switch.
Claim 9
Dependent Claim
57 words
The delay locked loop as recited in claim 7 , wherein the majority voter includes: a first to a third D flip-flops which are connected in series for receiving the output of the NOR gate of the majority voter; and an AND gate for performing a logic AND operation to the first to the third D flip-flops.
Claim 10
Dependent Claim
69 words
The delay locked loop as recited in claim 8 , wherein the buffer includes: a first input buffer for receiving the external clock signal though a positive terminal thereof and receiving an external clock bar signal through a negative terminal thereof; and a second input buffer for receiving the external clock signal though a negative terminal thereof and receiving the external clock bar signal through a positive terminal thereof.
Claim 11
Dependent Claim
111 words
A delay locked loop with at least one delay line, comprising: a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing a phase of the external clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
Claim 12
Dependent Claim
111 words
A delay locked loop with at least one delay line, comprising: a buffering means for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparing means for outputting a control signal to increase/decrease a delay amount after comparing a phase of the external clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing means for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
Claim 13
Dependent Claim
41 words
The delay locked loop as recited in claim 10 , wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
Claim 14
Dependent Claim
41 words
The delay locked loop as recited in claim 10 , wherein the multiplexing means selects the first clock in case that the control signal to increase the delay amount is inputted thereto when the second clock leads to the feedback clock.
Claim 15
Dependent Claim
66 words
The delay locked loop as recited in claim 10 , wherein the multiplexing means includes: a multiplexer selector for outputting a selection signal to select one between the first and the second clocks by using the output of the phase comparator and the output of the shift register; and a multiplexer for outputting the selected one between the first and the second clocks from the buffer.
Claim 16
Dependent Claim
133 words
The delay locked loop as recited in claim 13 , wherein the multiplexer selector includes: a first NAND gate for performing a logic NAND operation to the minimum shift bit signal and the command to decrease the delay amount; a second NAND gate for performing a logic NAND operation to the maximum shift bit signal and the command to increase the delay amount; a NOR gate for performing a logic NOR operation to the outputs of the first and the second NAND gates; a majority voter for outputting a predetermined signal when the output of the NOR gate is maintained for a predetermined time; a switch which is switched by the output of the majority voter and is reset by a reset signal; and a latch for latching the output of the switch.
Claim 17
Dependent Claim
106 words
A locking method of a delay locked loop with at least one delay line, comprising the steps of: a) outputting a first clock corresponding to an in-phase of an external clock and a second clock corresponding to an out-of-phase of the external clock; b) outputting a command to increase or decrease a delay amount by comparing a phase of the external clock with a phase of a feedback clock; c) outputting a shift signal in accordance with the command to increase or decrease the delay amount; and d) selecting one clock between the first and the second clocks by using the command and the shift signal.
Claim 18
Dependent Claim
106 words
A locking method of a delay locked loop with at least one delay line, comprising the steps of: a) outputting a first clock corresponding to an in-phase of an external clock and a second clock corresponding to an out-of-phase of the external clock; b) outputting a command to increase or decrease a delay amount by comparing a phase of the external clock with a phase of a feedback clock; c) outputting a shift signal in accordance with the command to increase or decrease the delay amount; and d) selecting one clock between the first and the second clocks by using the command and the shift signal.
Claim 19
Dependent Claim
52 words
The locking method as recited in claim 15 , wherein the step d) is performed to select the other clock in case that the command to decrease the delay amount is inputted when a phase of one of the first and the second clock passing through the delay line is delayed minimally.
Claim 20
Dependent Claim
52 words
The locking method as recited in claim 15 , wherein the step d) is performed to select the other clock in case that the command to increase the delay amount is inputted when a phase of one of the first and the second clock passing through the delay line is delayed maximally.
Claim 21
Dependent Claim
58 words
The locking method as recited in claim 15 , wherein the step d) includes the steps of: d1) outputting a selection signal for selecting one of the first and the second clocks by using the command and the shift signal; and d2) outputting the selected one of the first and the second clocks controlled by a control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-09-12 | 2009-03-14 | 2009-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-09-12 | 2013-03-14 | 2013-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-09-12 | 2017-03-14 | 2017-09-13 | $7700.00 | Window Closed / Lapsed |