US6898767B2
Expired / Lapsed
US
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Method and apparatus for custom design in a standard cell design environment
Assignee: Bell Semiconductor LLC
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Filing: 2002-05-09
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Granted: 2005-05-24
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Expires: 2022-05-09
Abstract
Abstract Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.
Inventors
- 👤 Duncan Halstead
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 08:05
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/323; G06F30/36; G06F30/367
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
86 words
A method of converting a SPICE netlist to a standard cell netlist comprising: converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells, standard cell timing reflects said timing information from said SPICE simulation.
Claim 2
Independent Claim
86 words
A method of converting a SPICE netlist to a standard cell netlist comprising: converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells, standard cell timing reflects said timing information from said SPICE simulation.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said step of converting further comprises: employing an LVS tool.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said step of converting further comprises: associating SPICE sub-circuit names with standard cell names.
Claim 5
Dependent Claim
15 words
The method of claim 1 further comprising: saving a file comprising said standard cell netlist.
Claim 6
Independent Claim
82 words
A method of converting a SPICE netlist to a standard cell netlist comprising: converting said SPICE netlist to an HDL netlist; synthesizing said HDL netlist to produce a standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells, standard cell timing reflects said timing information from said SPICE simulation.
Claim 7
Independent Claim
82 words
A method of converting a SPICE netlist to a standard cell netlist comprising: converting said SPICE netlist to an HDL netlist; synthesizing said HDL netlist to produce a standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells, standard cell timing reflects said timing information from said SPICE simulation.
Claim 8
Dependent Claim
15 words
The method of claim 5 further comprising: saving a file comprising said standard cell netlist.
Claim 9
Dependent Claim
13 words
The method of claim 5 wherein said HDL netlist is a Verilog netlist.
Claim 10
Independent Claim
135 words
A method of designing an integrated circuit containing standard cell and custom logic comprising: designing a first portion of said integrated circuit using HDL to produce an HDL netlist; designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist; synthesizing said HDL netlist to produce a first standard cell netlist; converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 11
Independent Claim
135 words
A method of designing an integrated circuit containing standard cell and custom logic comprising: designing a first portion of said integrated circuit using HDL to produce an HDL netlist; designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist; synthesizing said HDL netlist to produce a first standard cell netlist; converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 12
Dependent Claim
10 words
The method of claim 8 wherein said HDL is Verilog.
Claim 13
Dependent Claim
19 words
The method of claim 8 further comprising: simulating said first standard cell netlist and said second standard cell netlist.
Claim 14
Dependent Claim
23 words
The method of claim 8 further comprising: extracting fault coverage information from said first standard cell netlist and said second standard cell netlist.
Claim 15
Dependent Claim
21 words
The method of claim 8 further comprising: performing verification of said first standard cell netlist and said second standard cell netlist.
Claim 16
Independent Claim
135 words
A method of designing an integrated circuit containing standard cell and custom logic comprising: designing a first portion of said integrated circuit using HDL to produce a first HDL netlist; designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist; synthesizing said first HDL netlist to produce a first standard cell netlist; converting said SPICE netlist to a second HDL netlist; synthesizing said second HDL netlist to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 17
Independent Claim
135 words
A method of designing an integrated circuit containing standard cell and custom logic comprising: designing a first portion of said integrated circuit using HDL to produce a first HDL netlist; designing a second portion of said integrated circuit using SPICE to produce a SPICE netlist; synthesizing said first HDL netlist to produce a first standard cell netlist; converting said SPICE netlist to a second HDL netlist; synthesizing said second HDL netlist to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; simulating said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 18
Dependent Claim
18 words
The method of claim 13 wherein said first HDL netlist and said second HDL netlist are Verilog netlists.
Claim 19
Dependent Claim
19 words
The method of claim 13 further comprising: simulating said first standard cell netlist and said second standard cell netlist.
Claim 20
Dependent Claim
23 words
The method of claim 13 further comprising: extracting fault coverage information from said first standard cell netlist and said second standard cell netlist.
Claim 21
Dependent Claim
21 words
The method of claim 13 further comprising: performing verification of said first standard cell netlist and said second standard cell netlist.
Claim 22
Dependent Claim
143 words
An integrated circuit produced by the steps of: partitioning a design into a plurality of function blocks; designing a first one of said plurality of function blocks employing an HDL to produce an HDL netlist; synthesizing said HDL netlist to produce a first standard cell netlist; designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist; simulating said SPICE netlist; converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that, when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 23
Dependent Claim
143 words
An integrated circuit produced by the steps of: partitioning a design into a plurality of function blocks; designing a first one of said plurality of function blocks employing an HDL to produce an HDL netlist; synthesizing said HDL netlist to produce a first standard cell netlist; designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist; simulating said SPICE netlist; converting said SPICE netlist to logic functions; selecting standard cells that correspond to said logic functions to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that, when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 24
Dependent Claim
14 words
The integrated circuit of claim 18 wherein said HDL netlist is a Verilog netlist.
Claim 25
Dependent Claim
22 words
The integrated circuit of claim 18 further comprising: performing verification of said first standard cell netlist and said second standard cell netlist.
Claim 26
Dependent Claim
25 words
The integrated circuit of claim 18 further comprising: combining said first standard cell netlist and said second standard cell netlist and simulating the combined netlist.
Claim 27
Dependent Claim
15 words
The method of claim 21 further comprising: extracting fault coverage information from said combined netlist.
Claim 28
Dependent Claim
146 words
An integrated circuit produced by the steps of: partitioning a design into a plurality of function blocks; designing a first one of said plurality of function blocks employing an HDL to produce a first HDL netlist; synthesizing said first HDL netlist to produce a first standard cell netlist; designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist; simulating said SPICE netlist; converting said SPICE netlist to HDL to produce a second HDL netlist; synthesizing said second HDL netlist to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 29
Dependent Claim
146 words
An integrated circuit produced by the steps of: partitioning a design into a plurality of function blocks; designing a first one of said plurality of function blocks employing an HDL to produce a first HDL netlist; synthesizing said first HDL netlist to produce a first standard cell netlist; designing a second one of said plurality of function blocks employing SPICE to produce a SPICE netlist; simulating said SPICE netlist; converting said SPICE netlist to HDL to produce a second HDL netlist; synthesizing said second HDL netlist to produce a second standard cell netlist; extracting timing paths from said SPICE netlist; extracting timing information from the SPICE simulation; and creating a standard delay file using said timing information such that when said delay file is applied to said standard cells in said second standard cell netlist, standard cell timing reflects said timing information from said SPICE simulation.
Claim 30
Dependent Claim
19 words
The integrated circuit of claim 23 wherein said first HDL netlist and said second HDL netlist are Verilog netlists.
Claim 31
Dependent Claim
22 words
The integrated circuit of claim 23 further comprising: performing verification of said first standard cell netlist and said second standard cell netlist.
Claim 32
Dependent Claim
25 words
The integrated circuit of claim 23 further comprising: combining said first standard cell netlist and said second standard cell netlist and simulating the combined netlist.
Claim 33
Dependent Claim
15 words
The method of claim 26 further comprising: extracting fault coverage information from said combined netlist.
Claim 34
Independent Claim
82 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to logic functions; a second program that selects standard cells corresponding to said logic functions; a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 35
Independent Claim
82 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to logic functions; a second program that selects standard cells corresponding to said logic functions; a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 36
Independent Claim
90 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to logic functions; a second program that employs SPICE simulation information to select standard cells for said logic functions that reflect timing information; a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 37
Independent Claim
90 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to logic functions; a second program that employs SPICE simulation information to select standard cells for said logic functions that reflect timing information; a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 38
Independent Claim
91 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to an HDL netlist; a second program that synthesizes said HDL netlist into a standard cell netlist comprising a plurality of standard cells; and a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 39
Independent Claim
91 words
A system for converting a SPICE netlist to a standard cell netlist comprising: a computer; a first program that converts said SPICE netlist to an HDL netlist; a second program that synthesizes said HDL netlist into a standard cell netlist comprising a plurality of standard cells; and a third program that associates SPICE simulation timing information with signal paths of said standard cells and creates a standard delay file such that when said delay file is applied to said standard cells, timing of said standard cells reflects said SPICE simulation timing.
Claim 40
Dependent Claim
13 words
The system of claim 30 wherein said HDL netlist is a Verilog netlist.
References Cited (Backward Citations)
US5222030A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-05-23 | 2008-11-22 | 2009-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-05-23 | 2012-11-22 | 2013-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-05-23 | 2016-11-22 | 2017-05-24 | $7700.00 | Window Closed / Lapsed |