Adaptive active bias compensation technique for power amplifiers

Claim 2

A power amplifier circuit comprising: an FET amplifier including a gate terminal, a drain terminal and a source terminal; a current sensing element coupled to the drain terminal of the FET amplifier, said current sensing element providing a measured voltage signal indicative of a quiescent drain current of the FET amplifier; a switch coupled across the sensing element and being responsive to a switch signal, said switch signal closing the switch to bypass the sensing element when data is being amplified by the FET amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the FET amplifier; and a sample and hold circuit responsive to the measured voltage signal across the sensing element and a reference voltage signal, said sample and hold circuit forcing the measured voltage signal as close as possible to the reference voltage signal by a negative feedback through the amplifier circuit to regulate the current through the sensing element and set the quiescent drain current of the FET amplifier, said sample and hold circuit generating a DC bias voltage that is applied to the gate terminal of the FET amplifier.

Claim 3

The power amplifier circuit according to claim 1 wherein the sample and hold circuit is a digital sample and hold circuit.

Claim 4

The power amplifier circuit according to claim 2 wherein the sample and hold circuit includes a digital comparator that compares the measured voltage signal to the reference voltage signal, a digital counter responsive to a compared signal from the comparator, said counter being incremented up or down depending on the difference between the voltage signals, and a digital-to-analog converter responsive to a counter signal from the counter, said digital-to-analog converter providing the DC bias voltage.

Claim 5

The power amplifier circuit according to claim 2 wherein the sample and hold circuit includes a digital comparator that compares the measured voltage signal to the reference voltage signal, and a digital potentiometer responsive to a compared signal from the comparator, said digital potentiometer providing the DC bias voltage.

Claim 6

The power amplifier according to claim 1 wherein the sample and hold circuit is an analog circuit.

Claim 7

The power amplifier circuit according to claim 1 wherein the sample and hold circuit is responsive to the switch signal to prevent the sample and hold circuit from changing the DC bias voltage when data is being amplified by the FET amplifier.

Claim 8

The power amplifier circuit according to claim 1 further comprising a voltage level translator, said voltage level translator translating the measured voltage signal to a representative voltage signal referenced to ground.

Claim 9

The power amplifier circuit according to claim 1 wherein the current sensing element is a resistor.

Claim 10

The power amplifier circuit according to claim 8 wherein the resistor has a value in the range of 1-10 ohms.

Claim 11

The power amplifier circuit according to claim 1 wherein the switch is selected from the group consisting of a P-channel MOSFET, a bipolar junction transistor and a mechanical relay.

Claim 12

The power amplifier circuit according to claim 1 wherein the amplifier circuit is used in connection with a TDMA transmitter, where the switch signal is indicative of when the amplifier circuit is operating between data bursts.

Claim 13

A power amplifier circuit for amplifying an RF signal in a TDMA digital communications system, said circuit comprising: an FET amplifier including a gate terminal, a drain terminal and a source terminal; a current sensing resistor coupled to the drain terminal of the FET amplifier, said current sensing resistor providing a measured voltage signal indicative of a quiescent drain current of the FET amplifier; a switch coupled across the sensing resistor and being responsive to a TDMA signal indicative of when the communications system is between data bursts, said switch signal closing the switch to bypass the sensing resistor when data is being amplified by the FET amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the FET amplifier; and a digital sample and hold circuit responsive to the measured voltage signal and a reference voltage signal, said sample and hold signal including a digital comparator that compares the measured voltage signal to the reference voltage signal, a digital counter responsive to a compared signal from the comparator, said counter being incremented up or down depending on the difference between the voltage signals, and a digital-to-analog converter responsive to a counter signal from the counter, said digital-to-analog converter generating a DC bias voltage that is applied to the gate terminal of the FET amplifier to set the quiescent drain current.

Claim 14

A power amplifier circuit for amplifying an RF signal in a TDMA digital communications system, said circuit comprising: an FET amplifier including a gate terminal, a drain terminal and a source terminal; a current sensing resistor coupled to the drain terminal of the FET amplifier, said current sensing resistor providing a measured voltage signal indicative of a quiescent drain current of the FET amplifier; a switch coupled across the sensing resistor and being responsive to a TDMA signal indicative of when the communications system is between data bursts, said switch signal closing the switch to bypass the sensing resistor when data is being amplified by the FET amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the FET amplifier; and a digital sample and hold circuit responsive to the measured voltage signal and a reference voltage signal, said sample and hold signal including a digital comparator that compares the measured voltage signal to the reference voltage signal, a digital counter responsive to a compared signal from the comparator, said counter being incremented up or down depending on the difference between the voltage signals, and a digital-to-analog converter responsive to a counter signal from the counter, said digital-to-analog converter generating a DC bias voltage that is applied to the gate terminal of the FET amplifier to set the quiescent drain current.

Claim 15

The power amplifier circuit according to claim 12 further comprising a voltage level translator, said voltage level translator translating the measured voltage signal to a representative voltage signal referenced to ground.

Claim 16

The power amplifier circuit according to claim 12 wherein the resistor has a value in the range of 1-10 ohms.

Claim 17

The power amplifier circuit according to claim 12 wherein the switch is selected from the group consisting of a P-channel MOSFET, a bipolar junction transistor and a mechanical relay.

Claim 18

The power amplifier circuit according to claim 12 wherein the FET amplifier is an LDMOS FET amplifier.

Claim 21

The method according to claim 17 wherein selectively sensing the drain current of an FET amplifier includes using a resistor to provide a voltage drop indicative of the drain current.

Claim 22

The method according to claim 17 wherein comparing the sensed drain current to a reference signal and adjusting a DC bias voltage applied to a gate terminal of the FET amplifier are performed by a circuit selected from the group consisting of a digital sample and hold circuit and an analog sample and hold circuit.

Claim 23

The method according to claim 17 wherein the power amplifier is part of a TDMA transmitter.

Claim 24

A power amplifier circuit comprising: an amplifier; a current sensing element coupled to the amplifier, said current sensing element providing a measured voltage signal indicative of a quiescent drain current of the amplifier; and a switch coupled across the sensing element and being responsive to a switch signal, said switch signal closing the switch to bypass the sensing element when data is being amplified by the amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the amplifier.

Claim 25

A power amplifier circuit comprising: an amplifier; a current sensing element coupled to the amplifier, said current sensing element providing a measured voltage signal indicative of a quiescent drain current of the amplifier; and a switch coupled across the sensing element and being responsive to a switch signal, said switch signal closing the switch to bypass the sensing element when data is being amplified by the amplifier and opening the switch to sense the quiescent drain current when data is not being amplified by the amplifier.

Claim 26

The power amplifier circuit according to claim 21 further comprising a sample and hold circuit responsive to the measured voltage signal across the sensing element and a reference voltage signal, said sample and hold circuit forcing the measured voltage signal as close as possible to the reference voltage signal to regulate the current through the sensing element and set the quiescent drain circuit of the amplifier, said sample and hold circuit generating a DC bias voltage that is applied to the amplifier.

Claim 27

The power amplifier circuit according to claim 22 wherein the sample and hold circuit is a digital sample and hold circuit including a digital comparator that compares the measured voltage signal to the reference voltage signal, a digital counter responsive to a compared signal from the comparator, said counter being incremented up or down depending on the difference between the voltage signals, and a digital-to-analog converter responsive to a counter signal from the counter, said digital-to-analog converter providing the DC bias voltage.

Claim 28

The power amplifier circuit according to claim 22 wherein the sample and hold circuit is a digital sample and hold circuit that includes a digital comparator that compares the measured voltage signal to the reference voltage signal, and a digital potentiometer responsive to a compared signal from the comparator, said digital potentiometer providing the DC bias voltage.

Claim 29

The power amplifier circuit according to claim 22 wherein the sample and hold circuit is an analog circuit.

Claim 30

The power amplifier circuit according to claim 21 further comprising a voltage level translator, said voltage level translator translating the measured voltage signal to a representative voltage signal referenced to ground.

Claim 31

The power amplifier circuit according to claim 21 wherein the switch is selected from the group consisting of a P-channel MOSFET; a bipolar junction transistor and a mechanical relay.