US6882057B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quad flat no-lead chip carrier
Assignee: Via Technologies Inc
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Filing: 2003-09-19
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Granted: 2005-04-19
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Expires: 2023-09-19
Abstract
Abstract A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar through holes distributed around a chip-bonding region. The conductive columns are set up within the columnar through holes. The dielectric walls are set up between the sidewall of the conductive columns and the inner surface of the columnar through holes. The chip is electrically connected to the conductive columns via conductive wires. The bottom end of the conductive columns serves as input/output contacts for connecting with external contacts. The chip carrier is able to increase overall density of the input/output contacts and improve the electrical performance of the chip package.
Inventors
- 👤 Chi-Hsing Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:53
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/20; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W72/00; H10W72/50; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/754; H10W90/756
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
105 words
A quad flat no-lead chip carrier, comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate furthermore has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surfaces; a plurality of solid conductive columns set up within the respective columnar through holes; and a plurality of dielectric walls set up between the sidewall of the solid conductive columns and the inner surface of corresponding columnar through holes.
Claim 2
Dependent Claim
105 words
A quad flat no-lead chip carrier, comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate furthermore has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surfaces; a plurality of solid conductive columns set up within the respective columnar through holes; and a plurality of dielectric walls set up between the sidewall of the solid conductive columns and the inner surface of corresponding columnar through holes.
Claim 3
Dependent Claim
19 words
The chip carrier of claim 1 , wherein the first surface of the conductive plate is a rough surface.
Claim 4
Dependent Claim
20 words
The chip carrier of claim 1 , wherein the first surface of the conductive plate has an oxide layer thereon.
Claim 5
Dependent Claim
42 words
The chip carrier of claim 1 , wherein the carrier further comprises a solder mask layer set up on the second surface of the conductive plate that exposes a portion of an end surface of the conductive columns near the second surface.
Claim 6
Dependent Claim
152 words
A quad flat no-lead chip package, comprising: a chip carrier comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate furthermore has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surface; a plurality of solid conductive columns set up within the respective columnar through holes; and a plurality of dielectric walls set up between the sidewall of the solid conductive columns and the inner surface of the corresponding columnar through holes; a chip attached to the chip-bonding region on the first surface of the conductive plate; a plurality of first conductive wires electrically connecting the chip and the solid conductive columns; and an insulating material enclosing the chip and the first conductive wires.
Claim 7
Dependent Claim
152 words
A quad flat no-lead chip package, comprising: a chip carrier comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate furthermore has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surface; a plurality of solid conductive columns set up within the respective columnar through holes; and a plurality of dielectric walls set up between the sidewall of the solid conductive columns and the inner surface of the corresponding columnar through holes; a chip attached to the chip-bonding region on the first surface of the conductive plate; a plurality of first conductive wires electrically connecting the chip and the solid conductive columns; and an insulating material enclosing the chip and the first conductive wires.
Claim 8
Dependent Claim
26 words
The chip package of claim 5 , wherein the package further comprises at least a second conductive wire electrically connecting the chip to the conductive plate.
Claim 9
Dependent Claim
24 words
The chip package of claim 5 , wherein the package further comprises a conductive paste layer sandwiched between the chip and the conductive plate.
Claim 10
Dependent Claim
19 words
The chip package of claim 5 , wherein the first surface of the conductive plate is a rough surface.
Claim 11
Dependent Claim
20 words
The chip package of claim 5 , wherein the first surface of the conductive plate has an oxide layer thereon.
Claim 12
Dependent Claim
42 words
The chip package of claim 5 , wherein the carrier further comprises a solder mask layer set up on the second surface of the conductive plate that exposes a portion of an end surface of the conductive columns near the second surface.
Claim 13
Dependent Claim
139 words
A quad flat no-lead chip carrier, comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate further has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surfaces; a plurality of solid conductive columns disposed within the respective columnar through holes; a plurality of dielectric walls disposed between the sidewall of the conductive columns and the inner surface of the corresponding columnar through holes, wherein the dielectric walls are disposed within the corresponding columnar through holes; and a chip attached to the first surface of the conductive plate through a plurality of conductive wires connecting the chip and the conductive columns.
Claim 14
Dependent Claim
139 words
A quad flat no-lead chip carrier, comprising: a conductive plate having a first surface and a second surface, wherein the first surface has a chip-bonding region and the conductive plate further has a plurality of columnar through holes located on the periphery of the chip-bonding region such that the columnar through holes pass through the conductive plate to link up the first and the second surfaces; a plurality of solid conductive columns disposed within the respective columnar through holes; a plurality of dielectric walls disposed between the sidewall of the conductive columns and the inner surface of the corresponding columnar through holes, wherein the dielectric walls are disposed within the corresponding columnar through holes; and a chip attached to the first surface of the conductive plate through a plurality of conductive wires connecting the chip and the conductive columns.
Claim 15
Dependent Claim
22 words
The quad flat no-lead chip carrier of claim 11 , wherein the solid conductive columns completely fill the corresponding columnar through holes.
Claim 16
Dependent Claim
44 words
The quad flat no-lead chip carrier of claim 11 , wherein the carrier further comprises a solder mask layer configured on the second surface of the conductive plate that exposes a portion of an end surface of the conductive columns near the second surface.
Claim 17
Dependent Claim
22 words
The quad flat no-lead chip carrier of claim 11 , wherein the first surface of the conductive plate is a rough surface.
Claim 18
Dependent Claim
23 words
The quad flat no-lead chip carrier of claim 11 , wherein the first surface of the conductive plate has an oxide layer thereon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-04-18 | 2008-10-18 | 2009-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-04-18 | 2012-10-18 | 2013-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-04-18 | 2016-10-18 | 2017-04-19 | $7700.00 | Window Closed / Lapsed |