US6846618B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for improving critical dimension uniformity
Assignee: Winbond Electronics Corp
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Filing: 2002-08-08
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Granted: 2005-01-25
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Expires: 2022-08-08
Abstract
Abstract The present invention uses a double exposure and double etching method to improve critical dimension uniformity. A coating layer is formed on a wafer that includes a first area and a second area. The first area and the second area are separately patterned with different processing conditions. By means of this two-stage patterning, the CD uniformity between wafer center and wafer edge is successfully improved over the conventional single-stage patterning process. The fabrication yield is thus enhanced.
Inventors
- 👤 Yi-Yu Hsu
- 👤 Kuo-Chen Wang
- 👤 Yao-Ting Shao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:38
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/7055; G03F7/70558; G03F7/70425; G03F7/70605; G03F7/70616; G03F7/70625; G03F7/0035
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
123 words
A process for improving critical dimension uniformity suitable for use in integrated circuits, comprising: forming a coating layer on a wafer, the wafer including a first area and a second area; forming a first photoresist layer on the coating layer; subjecting the first photoresist layer in the first area to lithography process according to a pattern with a first lithography parameter; etching the coating layer in the first area with a first etching parameter; removing the first photoresist layer; forming a second photoresist layer on the coating layer; subjecting the second photoresist layer in the second area to lithography process according to the pattern with a second lithography parameter; and etching the coating layer in the second area with a second etching parameter.
Claim 2
Dependent Claim
123 words
A process for improving critical dimension uniformity suitable for use in integrated circuits, comprising: forming a coating layer on a wafer, the wafer including a first area and a second area; forming a first photoresist layer on the coating layer; subjecting the first photoresist layer in the first area to lithography process according to a pattern with a first lithography parameter; etching the coating layer in the first area with a first etching parameter; removing the first photoresist layer; forming a second photoresist layer on the coating layer; subjecting the second photoresist layer in the second area to lithography process according to the pattern with a second lithography parameter; and etching the coating layer in the second area with a second etching parameter.
Claim 3
Dependent Claim
30 words
The process as claimed in the claim 1 , wherein first lithography parameter applied to the first area is different from the second lithography parameter applied to the second area.
Claim 4
Dependent Claim
30 words
The process as claimed in claim 2 , wherein the first etching parameter applied to the first area is different from the second etching parameter applied to the second area.
Claim 5
Dependent Claim
43 words
The process as claimed in claim 2 , wherein the step of subjecting the first photoresist layer in the first area to lithography process with a first lithography parameter includes subjecting the first photoresist layer in the first area to exposure and developing.
Claim 6
Dependent Claim
43 words
The process as claimed in claim 2 , wherein the step of subjecting the second photoresist layer in the second area to lithography process with a second lithography parameter includes subjecting the second photoresist layer in the second area to exposure and developing.
Claim 7
Dependent Claim
30 words
The process as claimed in claim 5 , wherein the first area is a center area of the wafer, and the second area is an edge area of the wafer.
Claim 8
Dependent Claim
19 words
The process as claimed in claim 6 , wherein the center area and the edge area do not overlap.
Claim 9
Dependent Claim
19 words
The process as claimed in claim 1 , wherein the coating layer is a single layer formed by spin-coating.
Claim 10
Dependent Claim
18 words
The process as claimed in claim 1 , wherein the coating layer is multiple layers formed by spin-coating.
References Cited (Backward Citations)
US5691223A
Cited
US20030036005A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-01-25 | 2008-07-26 | 2009-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-01-25 | 2012-07-26 | 2013-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-01-25 | 2016-07-26 | 2017-01-25 | $7700.00 | Window Closed / Lapsed |